1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{GTimer, GatedValidRegNext, HasCircularQueuePtrHelper, SelectOne, XSPerfAccumulate, XSPerfHistogram} 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.issue.EntryBundles._ 11import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD} 12import xiangshan.backend.datapath.DataConfig._ 13import xiangshan.backend.datapath.DataSource 14import xiangshan.backend.fu.{FuConfig, FuType} 15import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 16import xiangshan.backend.rob.RobPtr 17import xiangshan.backend.datapath.NewPipelineConnect 18import xiangshan.backend.fu.vector.Bundles.VSew 19 20class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 21 override def shouldBeInlined: Boolean = false 22 23 implicit val iqParams: IssueBlockParams = params 24 lazy val module: IssueQueueImp = iqParams.schdType match { 25 case IntScheduler() => new IssueQueueIntImp(this) 26 case FpScheduler() => new IssueQueueFpImp(this) 27 case VfScheduler() => new IssueQueueVfImp(this) 28 case MemScheduler() => 29 if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this) 30 else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this) 31 else new IssueQueueIntImp(this) 32 case _ => null 33 } 34} 35 36class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle { 37 val empty = Output(Bool()) 38 val full = Output(Bool()) 39 val validCnt = Output(UInt(log2Ceil(numEntries + 1).W)) 40 val leftVec = Output(Vec(numEnq + 1, Bool())) 41} 42 43class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle 44 45class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 46 // Inputs 47 val flush = Flipped(ValidIO(new Redirect)) 48 val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst))) 49 50 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 51 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 52 val og2Resp = Option.when(params.needOg2Resp)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 53 val finalIssueResp = Option.when(params.LdExuCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 54 val memAddrIssueResp = Option.when(params.LdExuCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 55 val vecLoadIssueResp = Option.when(params.VlduCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 56 val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle) 57 val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle) 58 val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 59 val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 60 val vlFromIntIsZero = Input(Bool()) 61 val vlFromIntIsVlmax = Input(Bool()) 62 val vlFromVfIsZero = Input(Bool()) 63 val vlFromVfIsVlmax = Input(Bool()) 64 val og0Cancel = Input(ExuVec()) 65 val og1Cancel = Input(ExuVec()) 66 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 67 val replaceRCIdx = Option.when(params.needWriteRegCache)(Vec(params.numDeq, Input(UInt(RegCacheIdxWidth.W)))) 68 69 // Outputs 70 val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle 71 val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries)) 72 val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W))) 73 // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq)) 74 75 val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType 76 def allWakeUp = wakeupFromWB ++ wakeupFromIQ 77} 78 79class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams) 80 extends LazyModuleImp(wrapper) 81 with HasXSParameter { 82 83 override def desiredName: String = s"${params.getIQName}" 84 85 println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " + 86 s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " + 87 s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " + 88 s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " + 89 s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " + 90 s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}") 91 92 require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports") 93 require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports") 94 require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq") 95 require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq") 96 97 val deqFuCfgs : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs) 98 val allDeqFuCfgs : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs) 99 val fuCfgsCnt : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) } 100 val commonFuCfgs : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq 101 val wakeupFuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.wakeUpFuLatencyMap) 102 103 println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${wakeupFuLatencyMaps}") 104 println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}") 105 lazy val io = IO(new IssueQueueIO()) 106 107 // Modules 108 val entries = Module(new Entries) 109 val fuBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.latencyValMax > 0)(Module(new FuBusyTableWrite(x.fuLatencyMap))) } 110 val fuBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.latencyValMax > 0)(Module(new FuBusyTableRead(x.fuLatencyMap))) } 111 val intWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.intLatencyCertain)(Module(new FuBusyTableWrite(x.intFuLatencyMap))) } 112 val intWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.intLatencyCertain)(Module(new FuBusyTableRead(x.intFuLatencyMap))) } 113 val fpWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.fpLatencyCertain)(Module(new FuBusyTableWrite(x.fpFuLatencyMap))) } 114 val fpWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.fpLatencyCertain)(Module(new FuBusyTableRead(x.fpFuLatencyMap))) } 115 val vfWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.vfLatencyCertain)(Module(new FuBusyTableWrite(x.vfFuLatencyMap))) } 116 val vfWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.vfLatencyCertain)(Module(new FuBusyTableRead(x.vfFuLatencyMap))) } 117 val v0WbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.v0LatencyCertain)(Module(new FuBusyTableWrite(x.v0FuLatencyMap))) } 118 val v0WbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.v0LatencyCertain)(Module(new FuBusyTableRead(x.v0FuLatencyMap))) } 119 val vlWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.vlLatencyCertain)(Module(new FuBusyTableWrite(x.vlFuLatencyMap))) } 120 val vlWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.vlLatencyCertain)(Module(new FuBusyTableRead(x.vlFuLatencyMap))) } 121 122 class WakeupQueueFlush extends Bundle { 123 val redirect = ValidIO(new Redirect) 124 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO) 125 val og0Fail = Output(Bool()) 126 val og1Fail = Output(Bool()) 127 } 128 129 private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = { 130 val redirectFlush = exuInput.robIdx.needFlush(flush.redirect) 131 val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel) 132 val ogFailFlush = stage match { 133 case 1 => flush.og0Fail 134 case 2 => flush.og1Fail 135 case _ => false.B 136 } 137 redirectFlush || loadDependencyFlush || ogFailFlush 138 } 139 140 private def modificationFunc(exuInput: ExuInput): ExuInput = { 141 val newExuInput = WireDefault(exuInput) 142 newExuInput.loadDependency match { 143 case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1) 144 case None => 145 } 146 newExuInput 147 } 148 149 private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = { 150 val lastExuInput = WireDefault(exuInput) 151 val newExuInput = WireDefault(newInput) 152 newExuInput.elements.foreach { case (name, data) => 153 if (lastExuInput.elements.contains(name)) { 154 data := lastExuInput.elements(name) 155 } 156 } 157 if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) { 158 newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest) 159 } 160 if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) { 161 newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 162 } 163 if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) { 164 newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get) 165 } 166 if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) { 167 newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.vecWen.get) 168 } 169 if (newExuInput.v0WenCopy.nonEmpty && !lastExuInput.v0WenCopy.nonEmpty) { 170 newExuInput.v0WenCopy.get.foreach(_ := lastExuInput.v0Wen.get) 171 } 172 if (newExuInput.vlWenCopy.nonEmpty && !lastExuInput.vlWenCopy.nonEmpty) { 173 newExuInput.vlWenCopy.get.foreach(_ := lastExuInput.vlWen.get) 174 } 175 if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) { 176 newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get) 177 } 178 newExuInput 179 } 180 181 val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => Option.when(x.isIQWakeUpSource && !x.hasLoadExu)(Module( 182 new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc) 183 ))} 184 val deqBeforeDly = Wire(params.genIssueDecoupledBundle) 185 186 val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable) 187 val fpWbBusyTableIn = io.wbBusyTableRead.map(_.fpWbBusyTable) 188 val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable) 189 val v0WbBusyTableIn = io.wbBusyTableRead.map(_.v0WbBusyTable) 190 val vlWbBusyTableIn = io.wbBusyTableRead.map(_.vlWbBusyTable) 191 192 val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable) 193 val fpWbBusyTableOut = io.wbBusyTableWrite.map(_.fpWbBusyTable) 194 val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable) 195 val v0WbBusyTableOut = io.wbBusyTableWrite.map(_.v0WbBusyTable) 196 val vlWbBusyTableOut = io.wbBusyTableWrite.map(_.vlWbBusyTable) 197 198 val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet) 199 val fpDeqRespSetOut = io.wbBusyTableWrite.map(_.fpDeqRespSet) 200 val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet) 201 val v0DeqRespSetOut = io.wbBusyTableWrite.map(_.v0DeqRespSet) 202 val vlDeqRespSetOut = io.wbBusyTableWrite.map(_.vlDeqRespSet) 203 204 val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 205 val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 206 val fpWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 207 val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 208 val v0WbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 209 val vlWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 210 211 val s0_enqValidVec = io.enq.map(_.valid) 212 val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool())) 213 val s0_enqNotFlush = !io.flush.valid 214 val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits))) 215 val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady 216 217 218 val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool())) 219 val finalDeqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 220 221 val validVec = VecInit(entries.io.valid.asBools) 222 val issuedVec = VecInit(entries.io.issued.asBools) 223 val requestForTrans = VecInit(validVec.zip(issuedVec).map(x => x._1 && !x._2)) 224 val canIssueVec = VecInit(entries.io.canIssue.asBools) 225 dontTouch(canIssueVec) 226 val deqFirstIssueVec = entries.io.isFirstIssue 227 228 val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources 229 val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources))) 230 val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency 231 val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency))) 232 // (entryIdx)(srcIdx)(exuIdx) 233 val wakeUpL1ExuOH: Option[Vec[Vec[Vec[Bool]]]] = entries.io.srcWakeUpL1ExuOH 234 // (deqIdx)(srcIdx)(exuIdx) 235 val finalWakeUpL1ExuOH: Option[Vec[Vec[Vec[Bool]]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 236 237 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 238 val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 239 val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 240 val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 241 242 //deq 243 val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W)))) 244 val simpEntryOldestSel = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W))))) 245 val compEntryOldestSel = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W))))) 246 val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W)))) 247 val deqSelValidVec = Wire(Vec(params.numDeq, Bool())) 248 val deqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 249 val cancelDeqVec = Wire(Vec(params.numDeq, Bool())) 250 251 val subDeqSelValidVec = Option.when(params.deqFuSame)(Wire(Vec(params.numDeq, Bool()))) 252 val subDeqSelOHVec = Option.when(params.deqFuSame)(Wire(Vec(params.numDeq, UInt(params.numEntries.W)))) 253 val subDeqRequest = Option.when(params.deqFuSame)(Wire(UInt(params.numEntries.W))) 254 255 //trans 256 val simpEntryEnqSelVec = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numEnq, UInt(params.numSimp.W)))) 257 val compEntryEnqSelVec = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numEnq, UInt(params.numComp.W)))) 258 val othersEntryEnqSelVec = Option.when(params.isAllComp || params.isAllSimp)(Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W)))) 259 val simpAgeDetectRequest = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W)))) 260 simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get)) 261 262 // when vf exu (with og2) wake up int/mem iq (without og2), the wakeup signals should delay 1 cycle 263 // as vf exu's min latency is 1, we do not need consider og0cancel 264 val wakeupFromIQ = Wire(chiselTypeOf(io.wakeupFromIQ)) 265 wakeupFromIQ.zip(io.wakeupFromIQ).foreach { case (w, w_src) => 266 if (!params.inVfSchd && params.readVfRf && params.hasWakeupFromVf && w_src.bits.params.isVfExeUnit) { 267 val noCancel = !LoadShouldCancel(Some(w_src.bits.loadDependency), io.ldCancel) 268 w := RegNext(Mux(noCancel, w_src, 0.U.asTypeOf(w))) 269 w.bits.loadDependency.zip(w_src.bits.loadDependency).foreach{ case (ld, ld_src) => ld := RegNext(Mux(noCancel, ld_src << 1, 0.U.asTypeOf(ld))) } 270 } else { 271 w := w_src 272 } 273 } 274 275 /** 276 * Connection of [[entries]] 277 */ 278 entries.io match { case entriesIO: EntriesIO => 279 entriesIO.flush := io.flush 280 entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) => 281 enq.valid := s0_doEnqSelValidVec(enqIdx) 282 enq.bits.status.robIdx := s0_enqBits(enqIdx).robIdx 283 enq.bits.status.fuType := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType)) 284 val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size) 285 for(j <- 0 until numLsrc) { 286 enq.bits.status.srcStatus(j).psrc := s0_enqBits(enqIdx).psrc(j) 287 enq.bits.status.srcStatus(j).srcType := s0_enqBits(enqIdx).srcType(j) 288 enq.bits.status.srcStatus(j).srcState := (if (j < 3) { 289 Mux(SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U), 290 SrcState.rdy, 291 s0_enqBits(enqIdx).srcState(j)) 292 } else { 293 s0_enqBits(enqIdx).srcState(j) 294 }) 295 enq.bits.status.srcStatus(j).dataSources.value := (if (j < 3) { 296 MuxCase(DataSource.reg, Seq( 297 (SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U)) -> DataSource.zero, 298 SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)) -> DataSource.imm, 299 (SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U)) -> DataSource.v0, 300 )) 301 } else { 302 MuxCase(DataSource.reg, Seq( 303 SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)) -> DataSource.imm, 304 )) 305 }) 306 enq.bits.status.srcStatus(j).srcLoadDependency := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x << 1)) 307 if(params.hasIQWakeUp) { 308 enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get := 0.U.asTypeOf(ExuVec()) 309 } 310 enq.bits.status.srcStatus(j).useRegCache.foreach(_ := s0_enqBits(enqIdx).useRegCache(j)) 311 enq.bits.status.srcStatus(j).regCacheIdx.foreach(_ := s0_enqBits(enqIdx).regCacheIdx(j)) 312 } 313 enq.bits.status.blocked := false.B 314 enq.bits.status.issued := false.B 315 enq.bits.status.firstIssue := false.B 316 enq.bits.status.issueTimer := "b11".U 317 enq.bits.status.deqPortIdx := 0.U 318 enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm) 319 enq.bits.payload := s0_enqBits(enqIdx) 320 } 321 entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) => 322 og0Resp := io.og0Resp(i) 323 } 324 entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) => 325 og1Resp := io.og1Resp(i) 326 } 327 if (params.needOg2Resp) { 328 entriesIO.og2Resp.get.zipWithIndex.foreach { case (og2Resp, i) => 329 og2Resp := io.og2Resp.get(i) 330 } 331 } 332 if (params.isLdAddrIQ || params.isHyAddrIQ) { 333 entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) => 334 finalIssueResp := io.finalIssueResp.get(i) 335 } 336 entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) => 337 memAddrIssueResp := io.memAddrIssueResp.get(i) 338 } 339 } 340 if (params.isVecLduIQ) { 341 entriesIO.vecLdIn.get.resp.zipWithIndex.foreach { case (resp, i) => 342 resp := io.vecLoadIssueResp.get(i) 343 } 344 } 345 for(deqIdx <- 0 until params.numDeq) { 346 entriesIO.deqReady(deqIdx) := deqBeforeDly(deqIdx).ready 347 entriesIO.deqSelOH(deqIdx).valid := deqSelValidVec(deqIdx) 348 entriesIO.deqSelOH(deqIdx).bits := deqSelOHVec(deqIdx) 349 entriesIO.enqEntryOldestSel(deqIdx) := enqEntryOldestSel(deqIdx) 350 entriesIO.simpEntryOldestSel.foreach(_(deqIdx) := simpEntryOldestSel.get(deqIdx)) 351 entriesIO.compEntryOldestSel.foreach(_(deqIdx) := compEntryOldestSel.get(deqIdx)) 352 entriesIO.othersEntryOldestSel.foreach(_(deqIdx) := othersEntryOldestSel(deqIdx)) 353 entriesIO.subDeqRequest.foreach(_(deqIdx) := subDeqRequest.get) 354 entriesIO.subDeqSelOH.foreach(_(deqIdx) := subDeqSelOHVec.get(deqIdx)) 355 } 356 entriesIO.wakeUpFromWB := io.wakeupFromWB 357 entriesIO.wakeUpFromIQ := wakeupFromIQ 358 entriesIO.vlFromIntIsZero := io.vlFromIntIsZero 359 entriesIO.vlFromIntIsVlmax := io.vlFromIntIsVlmax 360 entriesIO.vlFromVfIsZero := io.vlFromVfIsZero 361 entriesIO.vlFromVfIsVlmax := io.vlFromVfIsVlmax 362 entriesIO.og0Cancel := io.og0Cancel 363 entriesIO.og1Cancel := io.og1Cancel 364 entriesIO.ldCancel := io.ldCancel 365 entriesIO.simpEntryDeqSelVec.foreach(_ := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits))) 366 //output 367 fuTypeVec := entriesIO.fuType 368 deqEntryVec := entriesIO.deqEntry 369 cancelDeqVec := entriesIO.cancelDeqVec 370 simpEntryEnqSelVec.foreach(_ := entriesIO.simpEntryEnqSelVec.get) 371 compEntryEnqSelVec.foreach(_ := entriesIO.compEntryEnqSelVec.get) 372 othersEntryEnqSelVec.foreach(_ := entriesIO.othersEntryEnqSelVec.get) 373 } 374 375 376 s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready} 377 378 protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType => 379 FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType)) 380 ).reverse) 381 382 // if deq port can accept the uop 383 protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 384 Cat(fuTypeVec.map(fuType => 385 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)) 386 ).reverse) 387 } 388 389 protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 390 fuTypeVec.map(fuType => 391 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 392 } 393 394 canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) => 395 val mergeFuBusy = { 396 if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i)) 397 else canIssueVec.asUInt 398 } 399 val mergeIntWbBusy = { 400 if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i)) 401 else mergeFuBusy 402 } 403 val mergefpWbBusy = { 404 if (fpWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~fpWbBusyTableMask(i)) 405 else mergeIntWbBusy 406 } 407 val mergeVfWbBusy = { 408 if (vfWbBusyTableRead(i).nonEmpty) mergefpWbBusy & (~vfWbBusyTableMask(i)) 409 else mergefpWbBusy 410 } 411 val mergeV0WbBusy = { 412 if (v0WbBusyTableRead(i).nonEmpty) mergeVfWbBusy & (~v0WbBusyTableMask(i)) 413 else mergeVfWbBusy 414 } 415 val mergeVlWbBusy = { 416 if (vlWbBusyTableRead(i).nonEmpty) mergeV0WbBusy & (~vlWbBusyTableMask(i)) 417 else mergeV0WbBusy 418 } 419 merge := mergeVlWbBusy 420 } 421 422 deqCanIssue.zipWithIndex.foreach { case (req, i) => 423 req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt 424 } 425 dontTouch(fuTypeVec) 426 dontTouch(canIssueMergeAllBusy) 427 dontTouch(deqCanIssue) 428 429 if (params.numDeq == 2) { 430 require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different") 431 } 432 433 if (params.numDeq == 2 && params.deqFuSame) { 434 val subDeqPolicy = Module(new DeqPolicy()) 435 436 enqEntryOldestSel := DontCare 437 438 if (params.isAllComp || params.isAllSimp) { 439 othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq, 440 enq = othersEntryEnqSelVec.get, 441 canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq) 442 ) 443 othersEntryOldestSel(1) := DontCare 444 445 subDeqPolicy.io.request := subDeqRequest.get 446 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 447 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits) 448 } 449 else { 450 simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq) 451 simpAgeDetectRequest.get(1) := DontCare 452 simpAgeDetectRequest.get(params.numDeq) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt 453 if (params.numEnq == 2) { 454 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 455 } 456 457 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 458 enq = simpEntryEnqSelVec.get, 459 canIssue = simpAgeDetectRequest.get 460 ) 461 462 compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp, 463 enq = compEntryEnqSelVec.get, 464 canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp) 465 ) 466 compEntryOldestSel.get(1) := DontCare 467 468 othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid 469 othersEntryOldestSel(0).bits := Cat( 470 compEntryOldestSel.get(0).bits, 471 Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits, 472 ) 473 othersEntryOldestSel(1) := DontCare 474 475 subDeqPolicy.io.request := Reverse(subDeqRequest.get) 476 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 477 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits)) 478 } 479 480 subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)) 481 482 deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1) 483 deqSelValidVec(1) := subDeqSelValidVec.get(0) 484 deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid, 485 Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)), 486 subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0) 487 deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1) 488 489 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 490 selValid := deqValid && deqOH.orR 491 selOH := deqOH 492 } 493 } 494 else { 495 enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq, 496 enq = VecInit(s0_doEnqSelValidVec), 497 canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0))) 498 ) 499 500 if (params.isAllComp || params.isAllSimp) { 501 othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq, 502 enq = othersEntryEnqSelVec.get, 503 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq))) 504 ) 505 506 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 507 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 508 selValid := false.B 509 selOH := 0.U.asTypeOf(selOH) 510 } else { 511 selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid 512 selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits) 513 } 514 } 515 } 516 else { 517 othersEntryOldestSel := DontCare 518 519 deqCanIssue.zipWithIndex.foreach { case (req, i) => 520 simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq) 521 } 522 simpAgeDetectRequest.get(params.numDeq) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt 523 if (params.numEnq == 2) { 524 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 525 } 526 527 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 528 enq = simpEntryEnqSelVec.get, 529 canIssue = simpAgeDetectRequest.get 530 ) 531 532 compEntryOldestSel.get := AgeDetector(numEntries = params.numComp, 533 enq = compEntryEnqSelVec.get, 534 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp))) 535 ) 536 537 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 538 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 539 selValid := false.B 540 selOH := 0.U.asTypeOf(selOH) 541 } else { 542 selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid 543 selOH := Cat( 544 compEntryOldestSel.get(i).bits, 545 Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits, 546 Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits 547 ) 548 } 549 } 550 } 551 552 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 553 selValid := deqValid 554 selOH := deqOH 555 } 556 } 557 558 val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle))) 559 560 toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) => 561 deqResp.valid := deqBeforeDly(i).valid 562 deqResp.bits.resp := RespType.success 563 deqResp.bits.robIdx := DontCare 564 deqResp.bits.sqIdx.foreach(_ := DontCare) 565 deqResp.bits.lqIdx.foreach(_ := DontCare) 566 deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType 567 deqResp.bits.uopIdx.foreach(_ := DontCare) 568 } 569 570 //fuBusyTable 571 fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) => 572 if(busyTableWrite.nonEmpty) { 573 val btwr = busyTableWrite.get 574 val btrd = busyTableRead.get 575 btwr.io.in.deqResp := toBusyTableDeqResp(i) 576 btwr.io.in.og0Resp := io.og0Resp(i) 577 btwr.io.in.og1Resp := io.og1Resp(i) 578 btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable 579 btrd.io.in.fuTypeRegVec := fuTypeVec 580 fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask 581 } 582 else { 583 fuBusyTableMask(i) := 0.U(params.numEntries.W) 584 } 585 } 586 587 //wbfuBusyTable write 588 intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 589 if(busyTableWrite.nonEmpty) { 590 val btwr = busyTableWrite.get 591 val bt = busyTable.get 592 val dq = deqResp.get 593 btwr.io.in.deqResp := toBusyTableDeqResp(i) 594 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.rfWen.getOrElse(false.B) 595 btwr.io.in.og0Resp := io.og0Resp(i) 596 btwr.io.in.og1Resp := io.og1Resp(i) 597 bt := btwr.io.out.fuBusyTable 598 dq := btwr.io.out.deqRespSet 599 } 600 } 601 602 fpWbBusyTableWrite.zip(fpWbBusyTableOut).zip(fpDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 603 if (busyTableWrite.nonEmpty) { 604 val btwr = busyTableWrite.get 605 val bt = busyTable.get 606 val dq = deqResp.get 607 btwr.io.in.deqResp := toBusyTableDeqResp(i) 608 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.fpWen.getOrElse(false.B) 609 btwr.io.in.og0Resp := io.og0Resp(i) 610 btwr.io.in.og1Resp := io.og1Resp(i) 611 bt := btwr.io.out.fuBusyTable 612 dq := btwr.io.out.deqRespSet 613 } 614 } 615 616 vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 617 if (busyTableWrite.nonEmpty) { 618 val btwr = busyTableWrite.get 619 val bt = busyTable.get 620 val dq = deqResp.get 621 btwr.io.in.deqResp := toBusyTableDeqResp(i) 622 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.vecWen.getOrElse(false.B) 623 btwr.io.in.og0Resp := io.og0Resp(i) 624 btwr.io.in.og1Resp := io.og1Resp(i) 625 bt := btwr.io.out.fuBusyTable 626 dq := btwr.io.out.deqRespSet 627 } 628 } 629 630 v0WbBusyTableWrite.zip(v0WbBusyTableOut).zip(v0DeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 631 if (busyTableWrite.nonEmpty) { 632 val btwr = busyTableWrite.get 633 val bt = busyTable.get 634 val dq = deqResp.get 635 btwr.io.in.deqResp := toBusyTableDeqResp(i) 636 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.v0Wen.getOrElse(false.B) 637 btwr.io.in.og0Resp := io.og0Resp(i) 638 btwr.io.in.og1Resp := io.og1Resp(i) 639 bt := btwr.io.out.fuBusyTable 640 dq := btwr.io.out.deqRespSet 641 } 642 } 643 644 vlWbBusyTableWrite.zip(vlWbBusyTableOut).zip(vlDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 645 if (busyTableWrite.nonEmpty) { 646 val btwr = busyTableWrite.get 647 val bt = busyTable.get 648 val dq = deqResp.get 649 btwr.io.in.deqResp := toBusyTableDeqResp(i) 650 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.vlWen.getOrElse(false.B) 651 btwr.io.in.og0Resp := io.og0Resp(i) 652 btwr.io.in.og1Resp := io.og1Resp(i) 653 bt := btwr.io.out.fuBusyTable 654 dq := btwr.io.out.deqRespSet 655 } 656 } 657 658 //wbfuBusyTable read 659 intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 660 if(busyTableRead.nonEmpty) { 661 val btrd = busyTableRead.get 662 val bt = busyTable.get 663 btrd.io.in.fuBusyTable := bt 664 btrd.io.in.fuTypeRegVec := fuTypeVec 665 intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 666 } 667 else { 668 intWbBusyTableMask(i) := 0.U(params.numEntries.W) 669 } 670 } 671 fpWbBusyTableRead.zip(fpWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 672 if (busyTableRead.nonEmpty) { 673 val btrd = busyTableRead.get 674 val bt = busyTable.get 675 btrd.io.in.fuBusyTable := bt 676 btrd.io.in.fuTypeRegVec := fuTypeVec 677 fpWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 678 } 679 else { 680 fpWbBusyTableMask(i) := 0.U(params.numEntries.W) 681 } 682 } 683 vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 684 if (busyTableRead.nonEmpty) { 685 val btrd = busyTableRead.get 686 val bt = busyTable.get 687 btrd.io.in.fuBusyTable := bt 688 btrd.io.in.fuTypeRegVec := fuTypeVec 689 vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 690 } 691 else { 692 vfWbBusyTableMask(i) := 0.U(params.numEntries.W) 693 } 694 } 695 v0WbBusyTableRead.zip(v0WbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 696 if (busyTableRead.nonEmpty) { 697 val btrd = busyTableRead.get 698 val bt = busyTable.get 699 btrd.io.in.fuBusyTable := bt 700 btrd.io.in.fuTypeRegVec := fuTypeVec 701 v0WbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 702 } 703 else { 704 v0WbBusyTableMask(i) := 0.U(params.numEntries.W) 705 } 706 } 707 vlWbBusyTableRead.zip(vlWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 708 if (busyTableRead.nonEmpty) { 709 val btrd = busyTableRead.get 710 val bt = busyTable.get 711 btrd.io.in.fuBusyTable := bt 712 btrd.io.in.fuTypeRegVec := fuTypeVec 713 vlWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 714 } 715 else { 716 vlWbBusyTableMask(i) := 0.U(params.numEntries.W) 717 } 718 } 719 720 wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) => 721 wakeUpQueueOption.foreach { 722 wakeUpQueue => 723 val flush = Wire(new WakeupQueueFlush) 724 flush.redirect := io.flush 725 flush.ldCancel := io.ldCancel 726 flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp) 727 flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp) 728 wakeUpQueue.io.flush := flush 729 wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid 730 wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common 731 wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U) 732 wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType) 733 } 734 } 735 736 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 737 deq.valid := finalDeqSelValidVec(i) && !cancelDeqVec(i) 738 deq.bits.addrOH := finalDeqSelOHVec(i) 739 deq.bits.common.isFirstIssue := deqFirstIssueVec(i) 740 deq.bits.common.iqIdx := OHToUInt(finalDeqSelOHVec(i)) 741 deq.bits.common.fuType := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 742 deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType 743 deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen) 744 deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen) 745 deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen) 746 deq.bits.common.v0Wen.foreach(_ := deqEntryVec(i).bits.payload.v0Wen) 747 deq.bits.common.vlWen.foreach(_ := deqEntryVec(i).bits.payload.vlWen) 748 deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe) 749 deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest 750 deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx 751 752 require(deq.bits.common.dataSources.size <= finalDataSources(i).size) 753 deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source} 754 deq.bits.common.l1ExuOH.foreach(_.zip(finalWakeUpL1ExuOH.get(i)).foreach { case (sink, source) => sink := source}) 755 deq.bits.common.srcTimer.foreach(_ := DontCare) 756 deq.bits.common.loadDependency.foreach(_.zip(finalLoadDependency(i)).foreach { case (sink, source) => sink := source}) 757 deq.bits.common.src := DontCare 758 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 759 760 deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) => 761 // psrc in status array can be pregIdx of IntRegFile or VfRegFile 762 rf.foreach(_.addr := psrc) 763 rf.foreach(_.srcType := srcType) 764 } 765 deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) => 766 sink := source 767 } 768 deq.bits.immType := deqEntryVec(i).bits.payload.selImm 769 deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U) 770 deq.bits.rcIdx.foreach(_ := deqEntryVec(i).bits.status.srcStatus.map(_.regCacheIdx.get)) 771 772 deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo 773 deq.bits.common.perfDebugInfo.selectTime := GTimer() 774 deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U 775 } 776 777 val deqDelay = Reg(params.genIssueValidBundle) 778 deqDelay.zip(deqBeforeDly).foreach { case (deqDly, deq) => 779 deqDly.valid := deq.valid 780 when(validVec.asUInt.orR) { 781 deqDly.bits := deq.bits 782 } 783 // deqBeforeDly.ready is always true 784 deq.ready := true.B 785 } 786 io.deqDelay.zip(deqDelay).foreach { case (sink, source) => 787 sink.valid := source.valid 788 sink.bits := source.bits 789 } 790 if(backendParams.debugEn) { 791 dontTouch(deqDelay) 792 dontTouch(io.deqDelay) 793 dontTouch(deqBeforeDly) 794 } 795 io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) => 796 if (wakeUpQueues(i).nonEmpty) { 797 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 798 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits) 799 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 800 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 801 wakeup.bits.rcDest.foreach(_ := io.replaceRCIdx.get(i)) 802 } else { 803 wakeup.valid := false.B 804 wakeup.bits := 0.U.asTypeOf(wakeup.bits) 805 } 806 if (wakeUpQueues(i).nonEmpty) { 807 wakeup.bits.rfWen := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B) 808 wakeup.bits.fpWen := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B) 809 wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B) 810 wakeup.bits.v0Wen := (if (wakeUpQueues(i).get.io.deq.bits.v0Wen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.v0Wen.get else false.B) 811 wakeup.bits.vlWen := (if (wakeUpQueues(i).get.io.deq.bits.vlWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vlWen.get else false.B) 812 } 813 814 if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){ 815 wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get 816 } 817 if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) { 818 wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get 819 } 820 if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) { 821 wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get 822 } 823 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) { 824 wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get 825 } 826 if (wakeUpQueues(i).nonEmpty && wakeup.bits.v0WenCopy.nonEmpty) { 827 wakeup.bits.v0WenCopy.get := wakeUpQueues(i).get.io.deq.bits.v0WenCopy.get 828 } 829 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vlWenCopy.nonEmpty) { 830 wakeup.bits.vlWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vlWenCopy.get 831 } 832 if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) { 833 wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get 834 } 835 } 836 837 // Todo: better counter implementation 838 private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _) 839 private val enqHasIssued = validVec.zip(issuedVec).take(params.numEnq).map(x => x._1 & x._2).reduce(_ | _) 840 private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq)) 841 private val othersValidCnt = PopCount(validVec.drop(params.numEnq)) 842 private val enqEntryValidCntDeq0 = PopCount( 843 validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b } 844 ) 845 private val othersValidCntDeq0 = PopCount( 846 validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b } 847 ) 848 private val enqEntryValidCntDeq1 = PopCount( 849 validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b } 850 ) 851 private val othersValidCntDeq1 = PopCount( 852 validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b } 853 ) 854 protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 855 io.enq.map(_.bits.fuType).map(fuType => 856 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 857 } 858 protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b }) 859 protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b }) 860 io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0) 861 io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1) 862 io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _) 863 for (i <- 0 until params.numEnq) { 864 io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U 865 } 866 private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W))) 867 othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 868 leftone := ~(1.U((params.numEntries - params.numEnq).W) << i) 869 } 870 private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _) 871 private val othersCanotIn = Wire(Bool()) 872 othersCanotIn := othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _) 873 // if has simp Entry, othersCanotIn will be simpCanotIn 874 if (params.numSimp > 0) { 875 val simpLeftOneCaseVec = Wire(Vec(params.numSimp, UInt((params.numSimp).W))) 876 simpLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 877 leftone := ~(1.U((params.numSimp).W) << i) 878 } 879 val simpLeftOne = simpLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt).reduce(_ | _) 880 val simpCanotIn = simpLeftOne || validVec.drop(params.numEnq).take(params.numSimp).reduce(_ & _) 881 othersCanotIn := simpCanotIn 882 } 883 io.enq.foreach(_.ready := (!othersCanotIn || !enqHasValid) && !enqHasIssued) 884 io.status.empty := !Cat(validVec).orR 885 io.status.full := othersCanotIn 886 io.status.validCnt := PopCount(validVec) 887 888 protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = { 889 Mux1H(wakeupFuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) }) 890 } 891 892 // issue perf counter 893 // enq count 894 XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire))) 895 XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire))) 896 XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) })) 897 XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) })) 898 XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire)) 899 XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire)) 900 // valid count 901 XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1) 902 XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1) 903 XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1) 904 // only split when more than 1 func type 905 if (params.getFuCfgs.size > 0) { 906 for (t <- FuType.functionNameMap.keys) { 907 val fuName = FuType.functionNameMap(t) 908 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 909 XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1) 910 } 911 } 912 } 913 // ready instr count 914 private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2)) 915 XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1) 916 // only split when more than 1 func type 917 if (params.getFuCfgs.size > 0) { 918 for (t <- FuType.functionNameMap.keys) { 919 val fuName = FuType.functionNameMap(t) 920 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 921 XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1) 922 } 923 } 924 } 925 926 // deq instr count 927 XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid))) 928 XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 929 XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid))) 930 XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 931 932 // deq instr data source count 933 XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq => 934 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 935 }.reduce(_ +& _)) 936 XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq => 937 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 938 }.reduce(_ +& _)) 939 XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq => 940 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 941 }.reduce(_ +& _)) 942 XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq => 943 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 944 }.reduce(_ +& _)) 945 946 XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq => 947 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 948 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 949 XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq => 950 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 951 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 952 XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq => 953 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 954 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 955 XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq => 956 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 957 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 958 959 // deq instr data source count for each futype 960 for (t <- FuType.functionNameMap.keys) { 961 val fuName = FuType.functionNameMap(t) 962 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 963 XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq => 964 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 965 }.reduce(_ +& _)) 966 XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq => 967 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 968 }.reduce(_ +& _)) 969 XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq => 970 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 971 }.reduce(_ +& _)) 972 XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq => 973 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 974 }.reduce(_ +& _)) 975 976 XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 977 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 978 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 979 XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq => 980 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 981 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 982 XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq => 983 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 984 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 985 XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 986 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 987 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 988 } 989 } 990} 991 992class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle { 993 val fastMatch = UInt(backendParams.LduCnt.W) 994 val fastImm = UInt(12.W) 995} 996 997class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO 998 999class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 1000 extends IssueQueueImp(wrapper) 1001{ 1002 io.suggestName("none") 1003 override lazy val io = IO(new IssueQueueIntIO).suggestName("io") 1004 1005 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 1006 deq.bits.common.pc.foreach(_ := DontCare) 1007 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 1008 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 1009 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 1010 deq.bits.common.predictInfo.foreach(x => { 1011 x.target := DontCare 1012 x.taken := deqEntryVec(i).bits.payload.pred_taken 1013 }) 1014 // for std 1015 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 1016 // for i2f 1017 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1018 }} 1019} 1020 1021class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 1022 extends IssueQueueImp(wrapper) 1023{ 1024 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 1025 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1026 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1027 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1028 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1029 }} 1030} 1031 1032class IssueQueueFpImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 1033 extends IssueQueueImp(wrapper) 1034{ 1035 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 1036 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1037 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1038 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1039 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1040 }} 1041} 1042 1043class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 1044 val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO(params.isVecMemIQ))) 1045 1046 // TODO: is still needed? 1047 val checkWait = new Bundle { 1048 val stIssuePtr = Input(new SqPtr) 1049 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 1050 } 1051 val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle)) 1052 1053 // load wakeup 1054 val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst()))) 1055 1056 // vector 1057 val sqDeqPtr = Option.when(params.isVecMemIQ)(Input(new SqPtr)) 1058 val lqDeqPtr = Option.when(params.isVecMemIQ)(Input(new LqPtr)) 1059} 1060 1061class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO { 1062 val memIO = Some(new IssueQueueMemBundle) 1063} 1064 1065class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 1066 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 1067 1068 require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " + 1069 s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 1070 println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 1071 1072 io.suggestName("none") 1073 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 1074 private val memIO = io.memIO.get 1075 1076 memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed? 1077 1078 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1079 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1080 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1081 slowResp.bits.sqIdx.foreach( _ := memIO.feedbackIO(i).feedbackSlow.bits.sqIdx) 1082 slowResp.bits.lqIdx.foreach( _ := memIO.feedbackIO(i).feedbackSlow.bits.lqIdx) 1083 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1084 slowResp.bits.fuType := DontCare 1085 } 1086 1087 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1088 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1089 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1090 fastResp.bits.sqIdx.foreach( _ := memIO.feedbackIO(i).feedbackFast.bits.sqIdx) 1091 fastResp.bits.lqIdx.foreach( _ := memIO.feedbackIO(i).feedbackFast.bits.lqIdx) 1092 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1093 fastResp.bits.fuType := DontCare 1094 } 1095 1096 // load wakeup 1097 val loadWakeUpIter = memIO.loadWakeUp.iterator 1098 io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) => 1099 if (param.hasLoadExu) { 1100 require(wakeUpQueues(i).isEmpty) 1101 val uop = loadWakeUpIter.next() 1102 1103 wakeup.valid := GatedValidRegNext(uop.fire) 1104 wakeup.bits.rfWen := (if (params.writeIntRf) GatedValidRegNext(uop.bits.rfWen && uop.fire) else false.B) 1105 wakeup.bits.fpWen := (if (params.writeFpRf) GatedValidRegNext(uop.bits.fpWen && uop.fire) else false.B) 1106 wakeup.bits.vecWen := (if (params.writeVecRf) GatedValidRegNext(uop.bits.vecWen && uop.fire) else false.B) 1107 wakeup.bits.v0Wen := (if (params.writeV0Rf) GatedValidRegNext(uop.bits.v0Wen && uop.fire) else false.B) 1108 wakeup.bits.vlWen := (if (params.writeVlRf) GatedValidRegNext(uop.bits.vlWen && uop.fire) else false.B) 1109 wakeup.bits.pdest := RegEnable(uop.bits.pdest, uop.fire) 1110 wakeup.bits.rcDest.foreach(_ := io.replaceRCIdx.get(i)) 1111 wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only 1112 1113 wakeup.bits.rfWenCopy .foreach(_.foreach(_ := (if (params.writeIntRf) GatedValidRegNext(uop.bits.rfWen && uop.fire) else false.B))) 1114 wakeup.bits.fpWenCopy .foreach(_.foreach(_ := (if (params.writeFpRf) GatedValidRegNext(uop.bits.fpWen && uop.fire) else false.B))) 1115 wakeup.bits.vecWenCopy.foreach(_.foreach(_ := (if (params.writeVecRf) GatedValidRegNext(uop.bits.vecWen && uop.fire) else false.B))) 1116 wakeup.bits.v0WenCopy .foreach(_.foreach(_ := (if (params.writeV0Rf) GatedValidRegNext(uop.bits.v0Wen && uop.fire) else false.B))) 1117 wakeup.bits.vlWenCopy .foreach(_.foreach(_ := (if (params.writeVlRf) GatedValidRegNext(uop.bits.vlWen && uop.fire) else false.B))) 1118 wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegEnable(uop.bits.pdest, uop.fire))) 1119 wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only 1120 1121 wakeup.bits.is0Lat := 0.U 1122 } 1123 } 1124 require(!loadWakeUpIter.hasNext) 1125 1126 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1127 deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit) 1128 deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx) 1129 deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit) 1130 deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict) 1131 deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid) 1132 deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx 1133 deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx 1134 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 1135 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 1136 } 1137} 1138 1139class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 1140 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 1141 1142 require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ") 1143 println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}") 1144 1145 io.suggestName("none") 1146 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 1147 private val memIO = io.memIO.get 1148 1149 require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports") 1150 1151 for (i <- entries.io.enq.indices) { 1152 entries.io.enq(i).bits.status match { case enqData => 1153 enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx 1154 enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx 1155 // MemAddrIQ also handle vector insts 1156 enqData.vecMem.get.numLsElem := s0_enqBits(i).numLsElem 1157 1158 val isFirstLoad = s0_enqBits(i).lqIdx <= memIO.lqDeqPtr.get 1159 val isVleff = s0_enqBits(i).vpu.isVleff 1160 enqData.blocked := !isFirstLoad && isVleff 1161 } 1162 } 1163 1164 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1165 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1166 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1167 slowResp.bits.sqIdx.get := memIO.feedbackIO(i).feedbackSlow.bits.sqIdx 1168 slowResp.bits.lqIdx.get := memIO.feedbackIO(i).feedbackSlow.bits.lqIdx 1169 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1170 slowResp.bits.fuType := DontCare 1171 slowResp.bits.uopIdx.get := DontCare 1172 } 1173 1174 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1175 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1176 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1177 fastResp.bits.sqIdx.get := memIO.feedbackIO(i).feedbackFast.bits.sqIdx 1178 fastResp.bits.lqIdx.get := memIO.feedbackIO(i).feedbackFast.bits.lqIdx 1179 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1180 fastResp.bits.fuType := DontCare 1181 fastResp.bits.uopIdx.get := DontCare 1182 } 1183 1184 entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get 1185 entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get 1186 1187 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1188 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx) 1189 deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx) 1190 deq.bits.common.numLsElem.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.numLsElem) 1191 if (params.isVecLduIQ) { 1192 deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr 1193 deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset 1194 } 1195 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1196 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1197 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1198 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1199 } 1200 1201 io.vecLoadIssueResp.foreach(dontTouch(_)) 1202} 1203