1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{GTimer, GatedValidRegNext, HasCircularQueuePtrHelper, SelectOne, XSPerfAccumulate, XSPerfHistogram} 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.issue.EntryBundles._ 11import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD} 12import xiangshan.backend.datapath.DataConfig._ 13import xiangshan.backend.datapath.DataSource 14import xiangshan.backend.fu.{FuConfig, FuType} 15import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 16import xiangshan.backend.rob.RobPtr 17import xiangshan.backend.datapath.NewPipelineConnect 18import xiangshan.backend.fu.vector.Bundles.VSew 19 20class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 21 override def shouldBeInlined: Boolean = false 22 23 implicit val iqParams: IssueBlockParams = params 24 lazy val module: IssueQueueImp = iqParams.schdType match { 25 case IntScheduler() => new IssueQueueIntImp(this) 26 case FpScheduler() => new IssueQueueFpImp(this) 27 case VfScheduler() => new IssueQueueVfImp(this) 28 case MemScheduler() => 29 if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this) 30 else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this) 31 else new IssueQueueIntImp(this) 32 case _ => null 33 } 34} 35 36class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle { 37 val empty = Output(Bool()) 38 val full = Output(Bool()) 39 val validCnt = Output(UInt(log2Ceil(numEntries + 1).W)) 40 val leftVec = Output(Vec(numEnq + 1, Bool())) 41} 42 43class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle 44 45class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 46 // Inputs 47 val flush = Flipped(ValidIO(new Redirect)) 48 val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst))) 49 50 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 51 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 52 val og2Resp = Option.when(params.needOg2Resp)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 53 val finalIssueResp = Option.when(params.LdExuCnt > 0 || params.VlduCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 54 val memAddrIssueResp = Option.when(params.LdExuCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 55 val vecLoadIssueResp = Option.when(params.VlduCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 56 val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle) 57 val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle) 58 val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 59 val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 60 val vlFromIntIsZero = Input(Bool()) 61 val vlFromIntIsVlmax = Input(Bool()) 62 val vlFromVfIsZero = Input(Bool()) 63 val vlFromVfIsVlmax = Input(Bool()) 64 val og0Cancel = Input(ExuVec()) 65 val og1Cancel = Input(ExuVec()) 66 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 67 val replaceRCIdx = Option.when(params.needWriteRegCache)(Vec(params.numDeq, Input(UInt(RegCacheIdxWidth.W)))) 68 69 // Outputs 70 val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle 71 val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries)) 72 val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W))) 73 // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq)) 74 75 val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType 76 def allWakeUp = wakeupFromWB ++ wakeupFromIQ 77} 78 79class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams) 80 extends LazyModuleImp(wrapper) 81 with HasXSParameter { 82 83 override def desiredName: String = s"${params.getIQName}" 84 85 println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " + 86 s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " + 87 s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " + 88 s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " + 89 s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " + 90 s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}") 91 92 require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports") 93 require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports") 94 require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq") 95 require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq") 96 97 val deqFuCfgs : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs) 98 val allDeqFuCfgs : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs) 99 val fuCfgsCnt : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) } 100 val commonFuCfgs : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq 101 val wakeupFuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.wakeUpFuLatencyMap) 102 103 println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${wakeupFuLatencyMaps}") 104 println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}") 105 if (params.hasIQWakeUp) { 106 val exuSourcesEncodeString = params.wakeUpSourceExuIdx.map(x => 1 << x).reduce(_ + _).toBinaryString 107 println(s"[IssueQueueImp] ${params.getIQName} exuSourcesWidth: ${ExuSource().value.getWidth}, " + 108 s"exuSourcesEncodeMask: ${"0" * (p(XSCoreParamsKey).backendParams.numExu - exuSourcesEncodeString.length) + exuSourcesEncodeString}") 109 } 110 111 lazy val io = IO(new IssueQueueIO()) 112 113 // Modules 114 val entries = Module(new Entries) 115 val fuBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.latencyValMax > 0)(Module(new FuBusyTableWrite(x.fuLatencyMap))) } 116 val fuBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.latencyValMax > 0)(Module(new FuBusyTableRead(x.fuLatencyMap))) } 117 val intWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.intLatencyCertain)(Module(new FuBusyTableWrite(x.intFuLatencyMap))) } 118 val intWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.intLatencyCertain)(Module(new FuBusyTableRead(x.intFuLatencyMap))) } 119 val fpWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.fpLatencyCertain)(Module(new FuBusyTableWrite(x.fpFuLatencyMap))) } 120 val fpWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.fpLatencyCertain)(Module(new FuBusyTableRead(x.fpFuLatencyMap))) } 121 val vfWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.vfLatencyCertain)(Module(new FuBusyTableWrite(x.vfFuLatencyMap))) } 122 val vfWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.vfLatencyCertain)(Module(new FuBusyTableRead(x.vfFuLatencyMap))) } 123 val v0WbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.v0LatencyCertain)(Module(new FuBusyTableWrite(x.v0FuLatencyMap))) } 124 val v0WbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.v0LatencyCertain)(Module(new FuBusyTableRead(x.v0FuLatencyMap))) } 125 val vlWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.vlLatencyCertain)(Module(new FuBusyTableWrite(x.vlFuLatencyMap))) } 126 val vlWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.vlLatencyCertain)(Module(new FuBusyTableRead(x.vlFuLatencyMap))) } 127 128 class WakeupQueueFlush extends Bundle { 129 val redirect = ValidIO(new Redirect) 130 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO) 131 val og0Fail = Output(Bool()) 132 val og1Fail = Output(Bool()) 133 } 134 135 private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = { 136 val redirectFlush = exuInput.robIdx.needFlush(flush.redirect) 137 val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel) 138 val ogFailFlush = stage match { 139 case 1 => flush.og0Fail 140 case 2 => flush.og1Fail 141 case _ => false.B 142 } 143 redirectFlush || loadDependencyFlush || ogFailFlush 144 } 145 146 private def modificationFunc(exuInput: ExuInput): ExuInput = { 147 val newExuInput = WireDefault(exuInput) 148 newExuInput.loadDependency match { 149 case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1) 150 case None => 151 } 152 newExuInput 153 } 154 155 private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = { 156 val lastExuInput = WireDefault(exuInput) 157 val newExuInput = WireDefault(newInput) 158 newExuInput.elements.foreach { case (name, data) => 159 if (lastExuInput.elements.contains(name)) { 160 data := lastExuInput.elements(name) 161 } 162 } 163 if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) { 164 newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest) 165 } 166 if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) { 167 newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 168 } 169 if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) { 170 newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get) 171 } 172 if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) { 173 newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.vecWen.get) 174 } 175 if (newExuInput.v0WenCopy.nonEmpty && !lastExuInput.v0WenCopy.nonEmpty) { 176 newExuInput.v0WenCopy.get.foreach(_ := lastExuInput.v0Wen.get) 177 } 178 if (newExuInput.vlWenCopy.nonEmpty && !lastExuInput.vlWenCopy.nonEmpty) { 179 newExuInput.vlWenCopy.get.foreach(_ := lastExuInput.vlWen.get) 180 } 181 if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) { 182 newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get) 183 } 184 newExuInput 185 } 186 187 val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => Option.when(x.isIQWakeUpSource && !x.hasLoadExu)(Module( 188 new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc) 189 ))} 190 val deqBeforeDly = Wire(params.genIssueDecoupledBundle) 191 192 val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable) 193 val fpWbBusyTableIn = io.wbBusyTableRead.map(_.fpWbBusyTable) 194 val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable) 195 val v0WbBusyTableIn = io.wbBusyTableRead.map(_.v0WbBusyTable) 196 val vlWbBusyTableIn = io.wbBusyTableRead.map(_.vlWbBusyTable) 197 198 val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable) 199 val fpWbBusyTableOut = io.wbBusyTableWrite.map(_.fpWbBusyTable) 200 val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable) 201 val v0WbBusyTableOut = io.wbBusyTableWrite.map(_.v0WbBusyTable) 202 val vlWbBusyTableOut = io.wbBusyTableWrite.map(_.vlWbBusyTable) 203 204 val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet) 205 val fpDeqRespSetOut = io.wbBusyTableWrite.map(_.fpDeqRespSet) 206 val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet) 207 val v0DeqRespSetOut = io.wbBusyTableWrite.map(_.v0DeqRespSet) 208 val vlDeqRespSetOut = io.wbBusyTableWrite.map(_.vlDeqRespSet) 209 210 val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 211 val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 212 val fpWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 213 val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 214 val v0WbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 215 val vlWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 216 217 val s0_enqValidVec = io.enq.map(_.valid) 218 val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool())) 219 val s0_enqNotFlush = !io.flush.valid 220 val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits))) 221 val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady 222 223 224 val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool())) 225 val finalDeqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 226 227 val validVec = VecInit(entries.io.valid.asBools) 228 val issuedVec = VecInit(entries.io.issued.asBools) 229 val requestForTrans = VecInit(validVec.zip(issuedVec).map(x => x._1 && !x._2)) 230 val canIssueVec = VecInit(entries.io.canIssue.asBools) 231 dontTouch(canIssueVec) 232 val deqFirstIssueVec = entries.io.isFirstIssue 233 234 val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources 235 val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources))) 236 val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency 237 val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency))) 238 // (entryIdx)(srcIdx) 239 val exuSources: Option[Vec[Vec[ExuSource]]] = entries.io.exuSources 240 // (deqIdx)(srcIdx) 241 val finalExuSources: Option[Vec[Vec[ExuSource]]] = exuSources.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 242 243 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 244 val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 245 val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 246 val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 247 248 //deq 249 val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W)))) 250 val simpEntryOldestSel = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W))))) 251 val compEntryOldestSel = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W))))) 252 val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W)))) 253 val deqSelValidVec = Wire(Vec(params.numDeq, Bool())) 254 val deqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 255 val cancelDeqVec = Wire(Vec(params.numDeq, Bool())) 256 257 val subDeqSelValidVec = Option.when(params.deqFuSame)(Wire(Vec(params.numDeq, Bool()))) 258 val subDeqSelOHVec = Option.when(params.deqFuSame)(Wire(Vec(params.numDeq, UInt(params.numEntries.W)))) 259 val subDeqRequest = Option.when(params.deqFuSame)(Wire(UInt(params.numEntries.W))) 260 261 //trans 262 val simpEntryEnqSelVec = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numEnq, UInt(params.numSimp.W)))) 263 val compEntryEnqSelVec = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numEnq, UInt(params.numComp.W)))) 264 val othersEntryEnqSelVec = Option.when(params.isAllComp || params.isAllSimp)(Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W)))) 265 val simpAgeDetectRequest = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W)))) 266 simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get)) 267 268 // when vf exu (with og2) wake up int/mem iq (without og2), the wakeup signals should delay 1 cycle 269 // as vf exu's min latency is 1, we do not need consider og0cancel 270 val wakeupFromIQ = Wire(chiselTypeOf(io.wakeupFromIQ)) 271 wakeupFromIQ.zip(io.wakeupFromIQ).foreach { case (w, w_src) => 272 if (!params.inVfSchd && params.readVfRf && params.hasWakeupFromVf && w_src.bits.params.isVfExeUnit) { 273 val noCancel = !LoadShouldCancel(Some(w_src.bits.loadDependency), io.ldCancel) 274 w := RegNext(Mux(noCancel, w_src, 0.U.asTypeOf(w))) 275 w.bits.loadDependency.zip(w_src.bits.loadDependency).foreach{ case (ld, ld_src) => ld := RegNext(Mux(noCancel, ld_src << 1, 0.U.asTypeOf(ld))) } 276 } else { 277 w := w_src 278 } 279 } 280 281 /** 282 * Connection of [[entries]] 283 */ 284 entries.io match { case entriesIO: EntriesIO => 285 entriesIO.flush := io.flush 286 entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) => 287 enq.valid := s0_doEnqSelValidVec(enqIdx) 288 enq.bits.status.robIdx := s0_enqBits(enqIdx).robIdx 289 enq.bits.status.fuType := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType)) 290 val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size) 291 for(j <- 0 until numLsrc) { 292 enq.bits.status.srcStatus(j).psrc := s0_enqBits(enqIdx).psrc(j) 293 enq.bits.status.srcStatus(j).srcType := s0_enqBits(enqIdx).srcType(j) 294 enq.bits.status.srcStatus(j).srcState := (if (j < 3) { 295 Mux(SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U), 296 SrcState.rdy, 297 s0_enqBits(enqIdx).srcState(j)) 298 } else { 299 s0_enqBits(enqIdx).srcState(j) 300 }) 301 enq.bits.status.srcStatus(j).dataSources.value := (if (j < 3) { 302 MuxCase(DataSource.reg, Seq( 303 (SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U)) -> DataSource.zero, 304 SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)) -> DataSource.imm, 305 (SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U)) -> DataSource.v0, 306 )) 307 } else { 308 MuxCase(DataSource.reg, Seq( 309 SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)) -> DataSource.imm, 310 )) 311 }) 312 enq.bits.status.srcStatus(j).srcLoadDependency := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x << 1)) 313 enq.bits.status.srcStatus(j).exuSources.foreach(_ := 0.U.asTypeOf(ExuSource())) 314 enq.bits.status.srcStatus(j).useRegCache.foreach(_ := s0_enqBits(enqIdx).useRegCache(j)) 315 enq.bits.status.srcStatus(j).regCacheIdx.foreach(_ := s0_enqBits(enqIdx).regCacheIdx(j)) 316 } 317 enq.bits.status.blocked := false.B 318 enq.bits.status.issued := false.B 319 enq.bits.status.firstIssue := false.B 320 enq.bits.status.issueTimer := "b11".U 321 enq.bits.status.deqPortIdx := 0.U 322 enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm) 323 enq.bits.payload := s0_enqBits(enqIdx) 324 } 325 entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) => 326 og0Resp := io.og0Resp(i) 327 } 328 entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) => 329 og1Resp := io.og1Resp(i) 330 } 331 if (params.needOg2Resp) { 332 entriesIO.og2Resp.get.zipWithIndex.foreach { case (og2Resp, i) => 333 og2Resp := io.og2Resp.get(i) 334 } 335 } 336 if (params.isLdAddrIQ || params.isHyAddrIQ) { 337 entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) => 338 finalIssueResp := io.finalIssueResp.get(i) 339 } 340 entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) => 341 memAddrIssueResp := io.memAddrIssueResp.get(i) 342 } 343 } 344 if (params.isVecLduIQ) { 345 entriesIO.vecLdIn.get.finalIssueResp.zipWithIndex.foreach { case (resp, i) => 346 resp := io.finalIssueResp.get(i) 347 } 348 entriesIO.vecLdIn.get.resp.zipWithIndex.foreach { case (resp, i) => 349 resp := io.vecLoadIssueResp.get(i) 350 } 351 } 352 for(deqIdx <- 0 until params.numDeq) { 353 entriesIO.deqReady(deqIdx) := deqBeforeDly(deqIdx).ready 354 entriesIO.deqSelOH(deqIdx).valid := deqSelValidVec(deqIdx) 355 entriesIO.deqSelOH(deqIdx).bits := deqSelOHVec(deqIdx) 356 entriesIO.enqEntryOldestSel(deqIdx) := enqEntryOldestSel(deqIdx) 357 entriesIO.simpEntryOldestSel.foreach(_(deqIdx) := simpEntryOldestSel.get(deqIdx)) 358 entriesIO.compEntryOldestSel.foreach(_(deqIdx) := compEntryOldestSel.get(deqIdx)) 359 entriesIO.othersEntryOldestSel.foreach(_(deqIdx) := othersEntryOldestSel(deqIdx)) 360 entriesIO.subDeqRequest.foreach(_(deqIdx) := subDeqRequest.get) 361 entriesIO.subDeqSelOH.foreach(_(deqIdx) := subDeqSelOHVec.get(deqIdx)) 362 } 363 entriesIO.wakeUpFromWB := io.wakeupFromWB 364 entriesIO.wakeUpFromIQ := wakeupFromIQ 365 entriesIO.vlFromIntIsZero := io.vlFromIntIsZero 366 entriesIO.vlFromIntIsVlmax := io.vlFromIntIsVlmax 367 entriesIO.vlFromVfIsZero := io.vlFromVfIsZero 368 entriesIO.vlFromVfIsVlmax := io.vlFromVfIsVlmax 369 entriesIO.og0Cancel := io.og0Cancel 370 entriesIO.og1Cancel := io.og1Cancel 371 entriesIO.ldCancel := io.ldCancel 372 entriesIO.simpEntryDeqSelVec.foreach(_ := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits))) 373 //output 374 fuTypeVec := entriesIO.fuType 375 deqEntryVec := entriesIO.deqEntry 376 cancelDeqVec := entriesIO.cancelDeqVec 377 simpEntryEnqSelVec.foreach(_ := entriesIO.simpEntryEnqSelVec.get) 378 compEntryEnqSelVec.foreach(_ := entriesIO.compEntryEnqSelVec.get) 379 othersEntryEnqSelVec.foreach(_ := entriesIO.othersEntryEnqSelVec.get) 380 } 381 382 383 s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready} 384 385 protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType => 386 FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType)) 387 ).reverse) 388 389 // if deq port can accept the uop 390 protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 391 Cat(fuTypeVec.map(fuType => 392 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)) 393 ).reverse) 394 } 395 396 protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 397 fuTypeVec.map(fuType => 398 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 399 } 400 401 canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) => 402 val mergeFuBusy = { 403 if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i)) 404 else canIssueVec.asUInt 405 } 406 val mergeIntWbBusy = { 407 if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i)) 408 else mergeFuBusy 409 } 410 val mergefpWbBusy = { 411 if (fpWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~fpWbBusyTableMask(i)) 412 else mergeIntWbBusy 413 } 414 val mergeVfWbBusy = { 415 if (vfWbBusyTableRead(i).nonEmpty) mergefpWbBusy & (~vfWbBusyTableMask(i)) 416 else mergefpWbBusy 417 } 418 val mergeV0WbBusy = { 419 if (v0WbBusyTableRead(i).nonEmpty) mergeVfWbBusy & (~v0WbBusyTableMask(i)) 420 else mergeVfWbBusy 421 } 422 val mergeVlWbBusy = { 423 if (vlWbBusyTableRead(i).nonEmpty) mergeV0WbBusy & (~vlWbBusyTableMask(i)) 424 else mergeV0WbBusy 425 } 426 merge := mergeVlWbBusy 427 } 428 429 deqCanIssue.zipWithIndex.foreach { case (req, i) => 430 req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt 431 } 432 dontTouch(fuTypeVec) 433 dontTouch(canIssueMergeAllBusy) 434 dontTouch(deqCanIssue) 435 436 if (params.numDeq == 2) { 437 require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different") 438 } 439 440 if (params.numDeq == 2 && params.deqFuSame) { 441 val subDeqPolicy = Module(new DeqPolicy()) 442 443 enqEntryOldestSel := DontCare 444 445 if (params.isAllComp || params.isAllSimp) { 446 othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq, 447 enq = othersEntryEnqSelVec.get, 448 canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq) 449 ) 450 othersEntryOldestSel(1) := DontCare 451 452 subDeqPolicy.io.request := subDeqRequest.get 453 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 454 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits) 455 } 456 else { 457 simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq) 458 simpAgeDetectRequest.get(1) := DontCare 459 simpAgeDetectRequest.get(params.numDeq) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt 460 if (params.numEnq == 2) { 461 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 462 } 463 464 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 465 enq = simpEntryEnqSelVec.get, 466 canIssue = simpAgeDetectRequest.get 467 ) 468 469 compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp, 470 enq = compEntryEnqSelVec.get, 471 canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp) 472 ) 473 compEntryOldestSel.get(1) := DontCare 474 475 othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid 476 othersEntryOldestSel(0).bits := Cat( 477 compEntryOldestSel.get(0).bits, 478 Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits, 479 ) 480 othersEntryOldestSel(1) := DontCare 481 482 subDeqPolicy.io.request := Reverse(subDeqRequest.get) 483 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 484 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits)) 485 } 486 487 subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)) 488 489 deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1) 490 deqSelValidVec(1) := subDeqSelValidVec.get(0) 491 deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid, 492 Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)), 493 subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0) 494 deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1) 495 496 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 497 selValid := deqValid && deqOH.orR 498 selOH := deqOH 499 } 500 } 501 else { 502 enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq, 503 enq = VecInit(s0_doEnqSelValidVec), 504 canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0))) 505 ) 506 507 if (params.isAllComp || params.isAllSimp) { 508 othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq, 509 enq = othersEntryEnqSelVec.get, 510 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq))) 511 ) 512 513 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 514 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 515 selValid := false.B 516 selOH := 0.U.asTypeOf(selOH) 517 } else { 518 selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid 519 selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits) 520 } 521 } 522 } 523 else { 524 othersEntryOldestSel := DontCare 525 526 deqCanIssue.zipWithIndex.foreach { case (req, i) => 527 simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq) 528 } 529 simpAgeDetectRequest.get(params.numDeq) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt 530 if (params.numEnq == 2) { 531 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 532 } 533 534 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 535 enq = simpEntryEnqSelVec.get, 536 canIssue = simpAgeDetectRequest.get 537 ) 538 539 compEntryOldestSel.get := AgeDetector(numEntries = params.numComp, 540 enq = compEntryEnqSelVec.get, 541 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp))) 542 ) 543 544 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 545 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 546 selValid := false.B 547 selOH := 0.U.asTypeOf(selOH) 548 } else { 549 selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid 550 selOH := Cat( 551 compEntryOldestSel.get(i).bits, 552 Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits, 553 Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits 554 ) 555 } 556 } 557 } 558 559 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 560 selValid := deqValid 561 selOH := deqOH 562 } 563 } 564 565 val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle))) 566 567 toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) => 568 deqResp.valid := deqBeforeDly(i).valid 569 deqResp.bits.resp := RespType.success 570 deqResp.bits.robIdx := DontCare 571 deqResp.bits.sqIdx.foreach(_ := DontCare) 572 deqResp.bits.lqIdx.foreach(_ := DontCare) 573 deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType 574 deqResp.bits.uopIdx.foreach(_ := DontCare) 575 } 576 577 //fuBusyTable 578 fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) => 579 if(busyTableWrite.nonEmpty) { 580 val btwr = busyTableWrite.get 581 val btrd = busyTableRead.get 582 btwr.io.in.deqResp := toBusyTableDeqResp(i) 583 btwr.io.in.og0Resp := io.og0Resp(i) 584 btwr.io.in.og1Resp := io.og1Resp(i) 585 btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable 586 btrd.io.in.fuTypeRegVec := fuTypeVec 587 fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask 588 } 589 else { 590 fuBusyTableMask(i) := 0.U(params.numEntries.W) 591 } 592 } 593 594 //wbfuBusyTable write 595 intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 596 if(busyTableWrite.nonEmpty) { 597 val btwr = busyTableWrite.get 598 val bt = busyTable.get 599 val dq = deqResp.get 600 btwr.io.in.deqResp := toBusyTableDeqResp(i) 601 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.rfWen.getOrElse(false.B) 602 btwr.io.in.og0Resp := io.og0Resp(i) 603 btwr.io.in.og1Resp := io.og1Resp(i) 604 bt := btwr.io.out.fuBusyTable 605 dq := btwr.io.out.deqRespSet 606 } 607 } 608 609 fpWbBusyTableWrite.zip(fpWbBusyTableOut).zip(fpDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 610 if (busyTableWrite.nonEmpty) { 611 val btwr = busyTableWrite.get 612 val bt = busyTable.get 613 val dq = deqResp.get 614 btwr.io.in.deqResp := toBusyTableDeqResp(i) 615 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.fpWen.getOrElse(false.B) 616 btwr.io.in.og0Resp := io.og0Resp(i) 617 btwr.io.in.og1Resp := io.og1Resp(i) 618 bt := btwr.io.out.fuBusyTable 619 dq := btwr.io.out.deqRespSet 620 } 621 } 622 623 vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 624 if (busyTableWrite.nonEmpty) { 625 val btwr = busyTableWrite.get 626 val bt = busyTable.get 627 val dq = deqResp.get 628 btwr.io.in.deqResp := toBusyTableDeqResp(i) 629 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.vecWen.getOrElse(false.B) 630 btwr.io.in.og0Resp := io.og0Resp(i) 631 btwr.io.in.og1Resp := io.og1Resp(i) 632 bt := btwr.io.out.fuBusyTable 633 dq := btwr.io.out.deqRespSet 634 } 635 } 636 637 v0WbBusyTableWrite.zip(v0WbBusyTableOut).zip(v0DeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 638 if (busyTableWrite.nonEmpty) { 639 val btwr = busyTableWrite.get 640 val bt = busyTable.get 641 val dq = deqResp.get 642 btwr.io.in.deqResp := toBusyTableDeqResp(i) 643 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.v0Wen.getOrElse(false.B) 644 btwr.io.in.og0Resp := io.og0Resp(i) 645 btwr.io.in.og1Resp := io.og1Resp(i) 646 bt := btwr.io.out.fuBusyTable 647 dq := btwr.io.out.deqRespSet 648 } 649 } 650 651 vlWbBusyTableWrite.zip(vlWbBusyTableOut).zip(vlDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 652 if (busyTableWrite.nonEmpty) { 653 val btwr = busyTableWrite.get 654 val bt = busyTable.get 655 val dq = deqResp.get 656 btwr.io.in.deqResp := toBusyTableDeqResp(i) 657 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.vlWen.getOrElse(false.B) 658 btwr.io.in.og0Resp := io.og0Resp(i) 659 btwr.io.in.og1Resp := io.og1Resp(i) 660 bt := btwr.io.out.fuBusyTable 661 dq := btwr.io.out.deqRespSet 662 } 663 } 664 665 //wbfuBusyTable read 666 intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 667 if(busyTableRead.nonEmpty) { 668 val btrd = busyTableRead.get 669 val bt = busyTable.get 670 btrd.io.in.fuBusyTable := bt 671 btrd.io.in.fuTypeRegVec := fuTypeVec 672 intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 673 } 674 else { 675 intWbBusyTableMask(i) := 0.U(params.numEntries.W) 676 } 677 } 678 fpWbBusyTableRead.zip(fpWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 679 if (busyTableRead.nonEmpty) { 680 val btrd = busyTableRead.get 681 val bt = busyTable.get 682 btrd.io.in.fuBusyTable := bt 683 btrd.io.in.fuTypeRegVec := fuTypeVec 684 fpWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 685 } 686 else { 687 fpWbBusyTableMask(i) := 0.U(params.numEntries.W) 688 } 689 } 690 vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 691 if (busyTableRead.nonEmpty) { 692 val btrd = busyTableRead.get 693 val bt = busyTable.get 694 btrd.io.in.fuBusyTable := bt 695 btrd.io.in.fuTypeRegVec := fuTypeVec 696 vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 697 } 698 else { 699 vfWbBusyTableMask(i) := 0.U(params.numEntries.W) 700 } 701 } 702 v0WbBusyTableRead.zip(v0WbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 703 if (busyTableRead.nonEmpty) { 704 val btrd = busyTableRead.get 705 val bt = busyTable.get 706 btrd.io.in.fuBusyTable := bt 707 btrd.io.in.fuTypeRegVec := fuTypeVec 708 v0WbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 709 } 710 else { 711 v0WbBusyTableMask(i) := 0.U(params.numEntries.W) 712 } 713 } 714 vlWbBusyTableRead.zip(vlWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 715 if (busyTableRead.nonEmpty) { 716 val btrd = busyTableRead.get 717 val bt = busyTable.get 718 btrd.io.in.fuBusyTable := bt 719 btrd.io.in.fuTypeRegVec := fuTypeVec 720 vlWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 721 } 722 else { 723 vlWbBusyTableMask(i) := 0.U(params.numEntries.W) 724 } 725 } 726 727 wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) => 728 wakeUpQueueOption.foreach { 729 wakeUpQueue => 730 val flush = Wire(new WakeupQueueFlush) 731 flush.redirect := io.flush 732 flush.ldCancel := io.ldCancel 733 flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp) 734 flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp) 735 wakeUpQueue.io.flush := flush 736 wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid 737 wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common 738 wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U) 739 wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType) 740 } 741 } 742 743 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 744 deq.valid := finalDeqSelValidVec(i) && !cancelDeqVec(i) 745 deq.bits.addrOH := finalDeqSelOHVec(i) 746 deq.bits.common.isFirstIssue := deqFirstIssueVec(i) 747 deq.bits.common.iqIdx := OHToUInt(finalDeqSelOHVec(i)) 748 deq.bits.common.fuType := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 749 deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType 750 deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen) 751 deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen) 752 deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen) 753 deq.bits.common.v0Wen.foreach(_ := deqEntryVec(i).bits.payload.v0Wen) 754 deq.bits.common.vlWen.foreach(_ := deqEntryVec(i).bits.payload.vlWen) 755 deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe) 756 deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest 757 deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx 758 759 require(deq.bits.common.dataSources.size <= finalDataSources(i).size) 760 deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source} 761 deq.bits.common.exuSources.foreach(_.zip(finalExuSources.get(i)).foreach { case (sink, source) => sink := source}) 762 deq.bits.common.srcTimer.foreach(_ := DontCare) 763 deq.bits.common.loadDependency.foreach(_.zip(finalLoadDependency(i)).foreach { case (sink, source) => sink := source}) 764 deq.bits.common.src := DontCare 765 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 766 767 deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) => 768 // psrc in status array can be pregIdx of IntRegFile or VfRegFile 769 rf.foreach(_.addr := psrc) 770 rf.foreach(_.srcType := srcType) 771 } 772 deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) => 773 sink := source 774 } 775 deq.bits.immType := deqEntryVec(i).bits.payload.selImm 776 deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U) 777 deq.bits.rcIdx.foreach(_ := deqEntryVec(i).bits.status.srcStatus.map(_.regCacheIdx.get)) 778 779 deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo 780 deq.bits.common.perfDebugInfo.selectTime := GTimer() 781 deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U 782 } 783 784 val deqDelay = Reg(params.genIssueValidBundle) 785 deqDelay.zip(deqBeforeDly).foreach { case (deqDly, deq) => 786 deqDly.valid := deq.valid 787 when(validVec.asUInt.orR) { 788 deqDly.bits := deq.bits 789 } 790 // deqBeforeDly.ready is always true 791 deq.ready := true.B 792 } 793 io.deqDelay.zip(deqDelay).foreach { case (sink, source) => 794 sink.valid := source.valid 795 sink.bits := source.bits 796 } 797 if(backendParams.debugEn) { 798 dontTouch(deqDelay) 799 dontTouch(io.deqDelay) 800 dontTouch(deqBeforeDly) 801 } 802 io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) => 803 if (wakeUpQueues(i).nonEmpty) { 804 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 805 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits) 806 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 807 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 808 wakeup.bits.rcDest.foreach(_ := io.replaceRCIdx.get(i)) 809 } else { 810 wakeup.valid := false.B 811 wakeup.bits := 0.U.asTypeOf(wakeup.bits) 812 } 813 if (wakeUpQueues(i).nonEmpty) { 814 wakeup.bits.rfWen := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B) 815 wakeup.bits.fpWen := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B) 816 wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B) 817 wakeup.bits.v0Wen := (if (wakeUpQueues(i).get.io.deq.bits.v0Wen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.v0Wen.get else false.B) 818 wakeup.bits.vlWen := (if (wakeUpQueues(i).get.io.deq.bits.vlWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vlWen.get else false.B) 819 } 820 821 if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){ 822 wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get 823 } 824 if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) { 825 wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get 826 } 827 if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) { 828 wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get 829 } 830 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) { 831 wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get 832 } 833 if (wakeUpQueues(i).nonEmpty && wakeup.bits.v0WenCopy.nonEmpty) { 834 wakeup.bits.v0WenCopy.get := wakeUpQueues(i).get.io.deq.bits.v0WenCopy.get 835 } 836 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vlWenCopy.nonEmpty) { 837 wakeup.bits.vlWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vlWenCopy.get 838 } 839 if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) { 840 wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get 841 } 842 } 843 844 // Todo: better counter implementation 845 private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _) 846 private val enqHasIssued = validVec.zip(issuedVec).take(params.numEnq).map(x => x._1 & x._2).reduce(_ | _) 847 private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq)) 848 private val othersValidCnt = PopCount(validVec.drop(params.numEnq)) 849 private val enqEntryValidCntDeq0 = PopCount( 850 validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b } 851 ) 852 private val othersValidCntDeq0 = PopCount( 853 validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b } 854 ) 855 private val enqEntryValidCntDeq1 = PopCount( 856 validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b } 857 ) 858 private val othersValidCntDeq1 = PopCount( 859 validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b } 860 ) 861 protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 862 io.enq.map(_.bits.fuType).map(fuType => 863 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 864 } 865 protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b }) 866 protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b }) 867 io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0) 868 io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1) 869 io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _) 870 for (i <- 0 until params.numEnq) { 871 io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U 872 } 873 private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W))) 874 othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 875 leftone := ~(1.U((params.numEntries - params.numEnq).W) << i) 876 } 877 private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _) 878 private val othersCanotIn = Wire(Bool()) 879 othersCanotIn := othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _) 880 // if has simp Entry, othersCanotIn will be simpCanotIn 881 if (params.numSimp > 0) { 882 val simpLeftOneCaseVec = Wire(Vec(params.numSimp, UInt((params.numSimp).W))) 883 simpLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 884 leftone := ~(1.U((params.numSimp).W) << i) 885 } 886 val simpLeftOne = simpLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt).reduce(_ | _) 887 val simpCanotIn = simpLeftOne || validVec.drop(params.numEnq).take(params.numSimp).reduce(_ & _) 888 othersCanotIn := simpCanotIn 889 } 890 io.enq.foreach(_.ready := (!othersCanotIn || !enqHasValid) && !enqHasIssued) 891 io.status.empty := !Cat(validVec).orR 892 io.status.full := othersCanotIn 893 io.status.validCnt := PopCount(validVec) 894 895 protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = { 896 Mux1H(wakeupFuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) }) 897 } 898 899 // issue perf counter 900 // enq count 901 XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire))) 902 XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire))) 903 XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) })) 904 XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) })) 905 XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire)) 906 XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire)) 907 // valid count 908 XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1) 909 XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1) 910 XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1) 911 // only split when more than 1 func type 912 if (params.getFuCfgs.size > 0) { 913 for (t <- FuType.functionNameMap.keys) { 914 val fuName = FuType.functionNameMap(t) 915 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 916 XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1) 917 } 918 } 919 } 920 // ready instr count 921 private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2)) 922 XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1) 923 // only split when more than 1 func type 924 if (params.getFuCfgs.size > 0) { 925 for (t <- FuType.functionNameMap.keys) { 926 val fuName = FuType.functionNameMap(t) 927 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 928 XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1) 929 } 930 } 931 } 932 933 // deq instr count 934 XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid))) 935 XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 936 XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid))) 937 XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 938 939 // deq instr data source count 940 XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq => 941 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 942 }.reduce(_ +& _)) 943 XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq => 944 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 945 }.reduce(_ +& _)) 946 XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq => 947 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 948 }.reduce(_ +& _)) 949 XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq => 950 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 951 }.reduce(_ +& _)) 952 953 XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq => 954 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 955 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 956 XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq => 957 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 958 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 959 XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq => 960 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 961 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 962 XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq => 963 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 964 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 965 966 // deq instr data source count for each futype 967 for (t <- FuType.functionNameMap.keys) { 968 val fuName = FuType.functionNameMap(t) 969 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 970 XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq => 971 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 972 }.reduce(_ +& _)) 973 XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq => 974 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 975 }.reduce(_ +& _)) 976 XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq => 977 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 978 }.reduce(_ +& _)) 979 XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq => 980 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 981 }.reduce(_ +& _)) 982 983 XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 984 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 985 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 986 XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq => 987 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 988 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 989 XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq => 990 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 991 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 992 XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 993 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 994 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 995 } 996 } 997} 998 999class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle { 1000 val fastMatch = UInt(backendParams.LduCnt.W) 1001 val fastImm = UInt(12.W) 1002} 1003 1004class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO 1005 1006class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 1007 extends IssueQueueImp(wrapper) 1008{ 1009 io.suggestName("none") 1010 override lazy val io = IO(new IssueQueueIntIO).suggestName("io") 1011 1012 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 1013 deq.bits.common.pc.foreach(_ := DontCare) 1014 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 1015 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 1016 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 1017 deq.bits.common.predictInfo.foreach(x => { 1018 x.target := DontCare 1019 x.taken := deqEntryVec(i).bits.payload.pred_taken 1020 }) 1021 // for std 1022 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 1023 // for i2f 1024 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1025 }} 1026} 1027 1028class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 1029 extends IssueQueueImp(wrapper) 1030{ 1031 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 1032 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1033 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1034 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1035 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1036 }} 1037} 1038 1039class IssueQueueFpImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 1040 extends IssueQueueImp(wrapper) 1041{ 1042 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 1043 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1044 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1045 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1046 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1047 }} 1048} 1049 1050class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 1051 val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO(params.isVecMemIQ))) 1052 1053 // TODO: is still needed? 1054 val checkWait = new Bundle { 1055 val stIssuePtr = Input(new SqPtr) 1056 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 1057 } 1058 val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle)) 1059 1060 // load wakeup 1061 val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst()))) 1062 1063 // vector 1064 val sqDeqPtr = Option.when(params.isVecMemIQ)(Input(new SqPtr)) 1065 val lqDeqPtr = Option.when(params.isVecMemIQ)(Input(new LqPtr)) 1066} 1067 1068class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO { 1069 val memIO = Some(new IssueQueueMemBundle) 1070} 1071 1072class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 1073 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 1074 1075 require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " + 1076 s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 1077 println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 1078 1079 io.suggestName("none") 1080 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 1081 private val memIO = io.memIO.get 1082 1083 memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed? 1084 1085 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1086 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1087 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1088 slowResp.bits.sqIdx.foreach( _ := memIO.feedbackIO(i).feedbackSlow.bits.sqIdx) 1089 slowResp.bits.lqIdx.foreach( _ := memIO.feedbackIO(i).feedbackSlow.bits.lqIdx) 1090 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1091 slowResp.bits.fuType := DontCare 1092 } 1093 1094 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1095 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1096 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1097 fastResp.bits.sqIdx.foreach( _ := memIO.feedbackIO(i).feedbackFast.bits.sqIdx) 1098 fastResp.bits.lqIdx.foreach( _ := memIO.feedbackIO(i).feedbackFast.bits.lqIdx) 1099 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1100 fastResp.bits.fuType := DontCare 1101 } 1102 1103 // load wakeup 1104 val loadWakeUpIter = memIO.loadWakeUp.iterator 1105 io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) => 1106 if (param.hasLoadExu) { 1107 require(wakeUpQueues(i).isEmpty) 1108 val uop = loadWakeUpIter.next() 1109 1110 wakeup.valid := GatedValidRegNext(uop.fire) 1111 wakeup.bits.rfWen := (if (params.writeIntRf) GatedValidRegNext(uop.bits.rfWen && uop.fire) else false.B) 1112 wakeup.bits.fpWen := (if (params.writeFpRf) GatedValidRegNext(uop.bits.fpWen && uop.fire) else false.B) 1113 wakeup.bits.vecWen := (if (params.writeVecRf) GatedValidRegNext(uop.bits.vecWen && uop.fire) else false.B) 1114 wakeup.bits.v0Wen := (if (params.writeV0Rf) GatedValidRegNext(uop.bits.v0Wen && uop.fire) else false.B) 1115 wakeup.bits.vlWen := (if (params.writeVlRf) GatedValidRegNext(uop.bits.vlWen && uop.fire) else false.B) 1116 wakeup.bits.pdest := RegEnable(uop.bits.pdest, uop.fire) 1117 wakeup.bits.rcDest.foreach(_ := io.replaceRCIdx.get(i)) 1118 wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only 1119 1120 wakeup.bits.rfWenCopy .foreach(_.foreach(_ := (if (params.writeIntRf) GatedValidRegNext(uop.bits.rfWen && uop.fire) else false.B))) 1121 wakeup.bits.fpWenCopy .foreach(_.foreach(_ := (if (params.writeFpRf) GatedValidRegNext(uop.bits.fpWen && uop.fire) else false.B))) 1122 wakeup.bits.vecWenCopy.foreach(_.foreach(_ := (if (params.writeVecRf) GatedValidRegNext(uop.bits.vecWen && uop.fire) else false.B))) 1123 wakeup.bits.v0WenCopy .foreach(_.foreach(_ := (if (params.writeV0Rf) GatedValidRegNext(uop.bits.v0Wen && uop.fire) else false.B))) 1124 wakeup.bits.vlWenCopy .foreach(_.foreach(_ := (if (params.writeVlRf) GatedValidRegNext(uop.bits.vlWen && uop.fire) else false.B))) 1125 wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegEnable(uop.bits.pdest, uop.fire))) 1126 wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only 1127 1128 wakeup.bits.is0Lat := 0.U 1129 } 1130 } 1131 require(!loadWakeUpIter.hasNext) 1132 1133 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1134 deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit) 1135 deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx) 1136 deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit) 1137 deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict) 1138 deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid) 1139 deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx 1140 deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx 1141 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 1142 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 1143 } 1144} 1145 1146class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 1147 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 1148 1149 require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ") 1150 println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}") 1151 1152 io.suggestName("none") 1153 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 1154 private val memIO = io.memIO.get 1155 1156 require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports") 1157 1158 for (i <- entries.io.enq.indices) { 1159 entries.io.enq(i).bits.status match { case enqData => 1160 enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx 1161 enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx 1162 // MemAddrIQ also handle vector insts 1163 enqData.vecMem.get.numLsElem := s0_enqBits(i).numLsElem 1164 1165 val isFirstLoad = s0_enqBits(i).lqIdx <= memIO.lqDeqPtr.get 1166 val isVleff = s0_enqBits(i).vpu.isVleff 1167 enqData.blocked := !isFirstLoad && isVleff 1168 } 1169 } 1170 1171 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1172 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1173 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1174 slowResp.bits.sqIdx.get := memIO.feedbackIO(i).feedbackSlow.bits.sqIdx 1175 slowResp.bits.lqIdx.get := memIO.feedbackIO(i).feedbackSlow.bits.lqIdx 1176 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1177 slowResp.bits.fuType := DontCare 1178 slowResp.bits.uopIdx.get := DontCare 1179 } 1180 1181 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1182 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1183 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1184 fastResp.bits.sqIdx.get := memIO.feedbackIO(i).feedbackFast.bits.sqIdx 1185 fastResp.bits.lqIdx.get := memIO.feedbackIO(i).feedbackFast.bits.lqIdx 1186 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1187 fastResp.bits.fuType := DontCare 1188 fastResp.bits.uopIdx.get := DontCare 1189 } 1190 1191 entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get 1192 entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get 1193 1194 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1195 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx) 1196 deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx) 1197 deq.bits.common.numLsElem.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.numLsElem) 1198 if (params.isVecLduIQ) { 1199 deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr 1200 deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset 1201 } 1202 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1203 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1204 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1205 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1206 } 1207 1208 io.vecLoadIssueResp.foreach(dontTouch(_)) 1209} 1210