1package xiangshan.backend.fu.vector.utils 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan.backend.fu.vector.Bundles.VSew 6 7class ScalaDupToVectorIO(vlen: Int) extends Bundle { 8 val in = Input(new Bundle { 9 val scalaData = UInt(64.W) // scala data would no more than 64 bits 10 val vsew = VSew() // 0: 8bits, 1: 16bits, 2: 32bits, 3: 64bits 11 }) 12 val out = Output(new Bundle { 13 val vecData = UInt(vlen.W) 14 }) 15} 16 17class ScalaDupToVector(vlen: Int) extends Module { 18 val io = IO(new ScalaDupToVectorIO(vlen)) 19 20 private val scalaData = io.in.scalaData 21 private val vsew = io.in.vsew 22 23 private val vecE8Data = Wire(Vec(vlen / 8, UInt( 8.W))) 24 private val vecE16Data = Wire(Vec(vlen / 16, UInt(16.W))) 25 private val vecE32Data = Wire(Vec(vlen / 32, UInt(32.W))) 26 private val vecE64Data = Wire(Vec(vlen / 64, UInt(64.W))) 27 28 vecE8Data := VecInit(Seq.fill(vlen / 8)(scalaData( 7, 0))) 29 vecE16Data := VecInit(Seq.fill(vlen / 16)(scalaData(15, 0))) 30 vecE32Data := VecInit(Seq.fill(vlen / 32)(scalaData(31, 0))) 31 vecE64Data := VecInit(Seq.fill(vlen / 64)(scalaData(63, 0))) 32 33 io.out.vecData := Mux1H(Seq( 34 (vsew === VSew.e8) -> vecE8Data.asUInt, 35 (vsew === VSew.e16) -> vecE16Data.asUInt, 36 (vsew === VSew.e32) -> vecE32Data.asUInt, 37 (vsew === VSew.e64) -> vecE64Data.asUInt, 38 )) 39} 40