xref: /XiangShan/src/main/scala/xiangshan/backend/fu/vector/utils/MaskExtrator.scala (revision 2df0274ee0d6eeb4d086dbcef739bf64670336f3) 
1package xiangshan.backend.fu.vector.utils
2
3import chisel3._
4import chisel3.util._
5import xiangshan.backend.fu.vector.Bundles.VSew
6
7class MaskExtractorIO(vlen: Int) extends Bundle {
8  private val numBytes = vlen / 8
9
10  val in = Input(new Bundle {
11    val mask = UInt(numBytes.W)
12    val vsew = VSew()
13  })
14  val out = Output(new Bundle {
15    val mask = UInt(numBytes.W)
16  })
17}
18
19class MaskExtractor(vlen: Int) extends Module {
20  private val numBytes = vlen / 8
21
22  val io = IO(new MaskExtractorIO(vlen))
23
24  private val mask = io.in.mask
25  private val vsew = io.in.vsew
26  private val extractedMask = Wire(UInt(vlen.W))
27
28  extractedMask := Mux1H(Seq(
29    (vsew === VSew.e8)  -> mask,
30    (vsew === VSew.e16) -> VecInit(mask.asBools.flatMap(Seq.fill(2)(_))).asUInt,
31    (vsew === VSew.e32) -> VecInit(mask.asBools.flatMap(Seq.fill(4)(_))).asUInt,
32    (vsew === VSew.e64) -> VecInit(mask.asBools.flatMap(Seq.fill(8)(_))).asUInt,
33  ))
34
35  io.out.mask := extractedMask
36}
37
38object MaskExtractor {
39  def apply(vlen: Int)(mask: UInt, vsew: UInt): UInt = {
40    val maskExtractor = Module(new MaskExtractor(vlen))
41    maskExtractor.io.in.mask := mask
42    maskExtractor.io.in.vsew := vsew
43    maskExtractor.io.out.mask
44  }
45}
46
47object VerilogMaskExtrator extends App {
48  println("Generating the MaskExtractor hardware")
49  emitVerilog(new MaskExtractor(128), Array("--full-stacktrace", "--target-dir", "build/MaskExtractor"))
50}
51