1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chisel3._ 20import chisel3.util._ 21import org.chipsalliance.cde.config._ 22import freechips.rocketchip.diplomacy._ 23import freechips.rocketchip.interrupts._ 24import freechips.rocketchip.tilelink._ 25import freechips.rocketchip.util._ 26import system.HasSoCParameter 27import device.{IMSICAsync, MsiInfoBundle} 28import coupledL2.tl2chi.{AsyncPortIO, CHIAsyncBridgeSource, PortIO} 29import utility.sram.{SramBroadcastBundle, SramMbistBundle} 30import utility.{DFTResetSignals, IntBuffer, ResetGen} 31import xiangshan.backend.trace.TraceCoreInterface 32 33// This module is used for XSNoCTop for async time domain and divide different 34// voltage domain. Everything in this module should be in the core clock domain 35// and higher voltage domain. 36class XSTileWrap()(implicit p: Parameters) extends LazyModule 37 with HasXSParameter 38 with HasSoCParameter 39{ 40 override def shouldBeInlined: Boolean = false 41 42 val tile = LazyModule(new XSTile()) 43 44 // interrupts sync 45 val clintIntNode = IntIdentityNode() 46 val debugIntNode = IntIdentityNode() 47 val plicIntNode = IntIdentityNode() 48 val beuIntNode = IntIdentityNode() 49 val nmiIntNode = IntIdentityNode() 50 tile.clint_int_node := IntBuffer(3, cdc = true) := clintIntNode 51 tile.debug_int_node := IntBuffer(3, cdc = true) := debugIntNode 52 tile.plic_int_node :*= IntBuffer(3, cdc = true) :*= plicIntNode 53 tile.nmi_int_node := IntBuffer(3, cdc = true) := nmiIntNode 54 beuIntNode := IntBuffer() := tile.beu_int_source 55 56 // seperate TL bus 57 println(s"SeperateTLBus = $SeperateTLBus") 58 println(s"EnableSeperateTLAsync = $EnableSeperateTLAsync") 59 // asynchronous bridge source node 60 val tlAsyncSourceOpt = Option.when(SeperateTLBus && EnableSeperateTLAsync)(LazyModule(new TLAsyncCrossingSource())) 61 tlAsyncSourceOpt.foreach(_.node := tile.sep_tl_opt.get) 62 // synchronous source node 63 val tlSyncSourceOpt = Option.when(SeperateTLBus && !EnableSeperateTLAsync)(TLTempNode()) 64 tlSyncSourceOpt.foreach(_ := tile.sep_tl_opt.get) 65 66 class XSTileWrapImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) { 67 val clock = IO(Input(Clock())) 68 val reset = IO(Input(AsyncReset())) 69 val noc_reset = EnableCHIAsyncBridge.map(_ => IO(Input(AsyncReset()))) 70 val soc_reset = IO(Input(AsyncReset())) 71 val io = IO(new Bundle { 72 val hartId = Input(UInt(hartIdLen.W)) 73 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 74 val reset_vector = Input(UInt(PAddrBits.W)) 75 val cpu_halt = Output(Bool()) 76 val cpu_crtical_error = Output(Bool()) 77 val hartResetReq = Input(Bool()) 78 val hartIsInReset = Output(Bool()) 79 val traceCoreInterface = new TraceCoreInterface 80 val debugTopDown = new Bundle { 81 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 82 val l3MissMatch = Input(Bool()) 83 } 84 val l3Miss = Input(Bool()) 85 val chi = EnableCHIAsyncBridge match { 86 case Some(param) => new AsyncPortIO(param) 87 case None => new PortIO 88 } 89 val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None 90 val clintTime = EnableClintAsyncBridge match { 91 case Some(param) => Flipped(new AsyncBundle(UInt(64.W), param)) 92 case None => Input(ValidIO(UInt(64.W))) 93 } 94 val sramTest = new Bundle() { 95 val mbist = Option.when(hasMbist)(Input(new SramMbistBundle)) 96 val mbistReset = Option.when(hasMbist)(Input(new DFTResetSignals())) 97 val sramCtl = Option.when(hasSramCtl)(Input(UInt(64.W))) 98 } 99 val l2_flush_en = Option.when(EnablePowerDown) (Output(Bool())) 100 val l2_flush_done = Option.when(EnablePowerDown) (Output(Bool())) 101 val pwrdown_req_n = Option.when(EnablePowerDown) (Input (Bool())) 102 val pwrdown_ack_n = Option.when(EnablePowerDown) (Output (Bool())) 103 val iso_en = Option.when(EnablePowerDown) (Input (Bool())) 104 }) 105 106 val reset_sync = withClockAndReset(clock, (reset.asBool || io.hartResetReq).asAsyncReset)(ResetGen(2, io.sramTest.mbistReset)) 107 val noc_reset_sync = EnableCHIAsyncBridge.map(_ => withClockAndReset(clock, noc_reset.get)(ResetGen(2, io.sramTest.mbistReset))) 108 val soc_reset_sync = withClockAndReset(clock, soc_reset)(ResetGen(2, io.sramTest.mbistReset)) 109 110 // override LazyRawModuleImp's clock and reset 111 childClock := clock 112 childReset := reset_sync 113 114 val imsicAsync = withClockAndReset(clock, reset_sync)(Module(new IMSICAsync())) 115 imsicAsync.i.msiInfo := io.msiInfo 116 117 tile.module.io.hartId := io.hartId 118 tile.module.io.msiInfo := imsicAsync.o.msiInfo 119 tile.module.io.reset_vector := io.reset_vector 120 tile.module.io.sramTest.mbist.zip(io.sramTest.mbist).foreach({case(a, b) => a := b}) 121 tile.module.io.sramTest.mbistReset.zip(io.sramTest.mbistReset).foreach({case(a, b) => a := b}) 122 tile.module.io.sramTest.sramCtl.zip(io.sramTest.sramCtl).foreach({case(a, b) => a := b}) 123 io.cpu_halt := tile.module.io.cpu_halt 124 io.cpu_crtical_error := tile.module.io.cpu_crtical_error 125 io.hartIsInReset := tile.module.io.hartIsInReset 126 io.traceCoreInterface <> tile.module.io.traceCoreInterface 127 io.debugTopDown <> tile.module.io.debugTopDown 128 tile.module.io.l3Miss := io.l3Miss 129 tile.module.io.nodeID.foreach(_ := io.nodeID.get) 130 io.l2_flush_en.foreach { _ := tile.module.io.l2_flush_en.getOrElse(false.B) } 131 io.l2_flush_done.foreach { _ := tile.module.io.l2_flush_done.getOrElse(false.B) } 132 io.pwrdown_ack_n.foreach { _ := true.B } 133 134 // CLINT Async Queue Sink 135 EnableClintAsyncBridge match { 136 case Some(param) => 137 val sink = withClockAndReset(clock, soc_reset_sync)(Module(new AsyncQueueSink(UInt(64.W), param))) 138 sink.io.async <> io.clintTime 139 sink.io.deq.ready := true.B 140 tile.module.io.clintTime.valid := sink.io.deq.valid 141 tile.module.io.clintTime.bits := sink.io.deq.bits 142 case None => 143 tile.module.io.clintTime := io.clintTime 144 } 145 146 // CHI Async Queue Source 147 EnableCHIAsyncBridge match { 148 case Some(param) => 149 val source = withClockAndReset(clock, noc_reset_sync.get)(Module(new CHIAsyncBridgeSource(param))) 150 source.io.enq <> tile.module.io.chi.get 151 io.chi <> source.io.async 152 case None => 153 require(enableCHI) 154 io.chi <> tile.module.io.chi.get 155 } 156 157 // Seperate DebugModule TL Async Queue Source 158 if (SeperateTLBus && EnableSeperateTLAsync) { 159 tlAsyncSourceOpt.get.module.clock := clock 160 tlAsyncSourceOpt.get.module.reset := soc_reset_sync 161 } 162 163 withClockAndReset(clock, reset_sync) { 164 // Modules are reset one by one 165 // reset ----> SYNC --> XSTile 166 val resetChain = Seq(Seq(tile.module)) 167 ResetGen(resetChain, reset_sync, !debugOpts.FPGAPlatform, io.sramTest.mbistReset) 168 } 169 dontTouch(io.hartId) 170 dontTouch(io.msiInfo) 171 } 172 lazy val module = new XSTileWrapImp(this) 173} 174