xref: /XiangShan/src/main/scala/xiangshan/XSTileWrap.scala (revision c08f49a0dbf6e9ef292ad0b90193d3946d11b1b6) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan
18
19import chisel3._
20import chisel3.util._
21import org.chipsalliance.cde.config._
22import freechips.rocketchip.diplomacy._
23import freechips.rocketchip.interrupts._
24import freechips.rocketchip.util._
25import system.HasSoCParameter
26import device.{IMSICAsync, MsiInfoBundle}
27import coupledL2.tl2chi.{PortIO, AsyncPortIO, CHIAsyncBridgeSource}
28import utility.{IntBuffer, ResetGen}
29
30// This module is used for XSNoCTop for async time domain and divide different
31// voltage domain. Everything in this module should be in the core clock domain
32// and higher voltage domain.
33class XSTileWrap()(implicit p: Parameters) extends LazyModule
34  with HasXSParameter
35  with HasSoCParameter
36{
37  override def shouldBeInlined: Boolean = false
38
39  val tile = LazyModule(new XSTile())
40
41  // interrupts sync
42  val clintIntNode = IntIdentityNode()
43  val debugIntNode = IntIdentityNode()
44  val plicIntNode = IntIdentityNode()
45  val beuIntNode = IntIdentityNode()
46  tile.clint_int_node := IntBuffer(3, cdc = true) := clintIntNode
47  tile.debug_int_node := IntBuffer(3, cdc = true) := debugIntNode
48  tile.plic_int_node :*= IntBuffer(3, cdc = true) :*= plicIntNode
49  beuIntNode := IntBuffer() := tile.beu_int_source
50  class XSTileWrapImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) {
51    val clock = IO(Input(Clock()))
52    val reset = IO(Input(AsyncReset()))
53    val noc_reset = EnableCHIAsyncBridge.map(_ => IO(Input(AsyncReset())))
54    val soc_reset = IO(Input(AsyncReset()))
55    val io = IO(new Bundle {
56      val hartId = Input(UInt(hartIdLen.W))
57      val msiInfo = Input(ValidIO(new MsiInfoBundle))
58      val reset_vector = Input(UInt(PAddrBits.W))
59      val cpu_halt = Output(Bool())
60      val hartIsInReset = Output(Bool())
61      val debugTopDown = new Bundle {
62        val robHeadPaddr = Valid(UInt(PAddrBits.W))
63        val l3MissMatch = Input(Bool())
64      }
65      val chi = EnableCHIAsyncBridge match {
66        case Some(param) => new AsyncPortIO(param)
67        case None => new PortIO
68      }
69      val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None
70      val clintTime = EnableClintAsyncBridge match {
71        case Some(param) => Flipped(new AsyncBundle(UInt(64.W), param))
72        case None => Input(ValidIO(UInt(64.W)))
73      }
74    })
75
76    val reset_sync = withClockAndReset(clock, reset)(ResetGen())
77    val noc_reset_sync = EnableCHIAsyncBridge.map(_ => withClockAndReset(clock, noc_reset.get)(ResetGen()))
78    val soc_reset_sync = withClockAndReset(clock, soc_reset)(ResetGen())
79
80    // override LazyRawModuleImp's clock and reset
81    childClock := clock
82    childReset := reset_sync
83
84    val imsicAsync = withClockAndReset(clock, reset_sync)(Module(new IMSICAsync()))
85    imsicAsync.i.msiInfo := io.msiInfo
86
87    tile.module.io.hartId := io.hartId
88    tile.module.io.msiInfo := imsicAsync.o.msiInfo
89    tile.module.io.reset_vector := io.reset_vector
90    io.cpu_halt := tile.module.io.cpu_halt
91    io.hartIsInReset := tile.module.io.hartIsInReset
92    io.debugTopDown <> tile.module.io.debugTopDown
93    tile.module.io.nodeID.foreach(_ := io.nodeID.get)
94
95    // CLINT Async Queue Sink
96    EnableClintAsyncBridge match {
97      case Some(param) =>
98        val sink = withClockAndReset(clock, soc_reset_sync)(Module(new AsyncQueueSink(UInt(64.W), param)))
99        sink.io.async <> io.clintTime
100        sink.io.deq.ready := true.B
101        tile.module.io.clintTime.valid := sink.io.deq.valid
102        tile.module.io.clintTime.bits := sink.io.deq.bits
103      case None =>
104        tile.module.io.clintTime := io.clintTime
105    }
106
107    // CHI Async Queue Source
108    EnableCHIAsyncBridge match {
109      case Some(param) =>
110        val source = withClockAndReset(clock, noc_reset_sync.get)(Module(new CHIAsyncBridgeSource(param)))
111        source.io.enq <> tile.module.io.chi.get
112        io.chi <> source.io.async
113      case None =>
114        require(enableCHI)
115        io.chi <> tile.module.io.chi.get
116    }
117
118    withClockAndReset(clock, reset_sync) {
119      // Modules are reset one by one
120      // reset ----> SYNC --> XSTile
121      val resetChain = Seq(Seq(tile.module))
122      ResetGen(resetChain, reset_sync, !debugOpts.FPGAPlatform)
123    }
124    dontTouch(io.hartId)
125    dontTouch(io.msiInfo)
126  }
127  lazy val module = new XSTileWrapImp(this)
128}
129