xref: /XiangShan/src/main/scala/xiangshan/XSTileWrap.scala (revision b7a634950d492998c81ae5fa4ea510d1b69f0b22) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan
18
19import chisel3._
20import chisel3.util._
21import org.chipsalliance.cde.config._
22import freechips.rocketchip.diplomacy._
23import freechips.rocketchip.interrupts._
24import freechips.rocketchip.util._
25import system.HasSoCParameter
26import device.{IMSICAsync, MsiInfoBundle}
27import coupledL2.tl2chi.{PortIO, AsyncPortIO, CHIAsyncBridgeSource}
28import utility.{IntBuffer, ResetGen}
29import xiangshan.backend.trace.TraceCoreInterface
30
31// This module is used for XSNoCTop for async time domain and divide different
32// voltage domain. Everything in this module should be in the core clock domain
33// and higher voltage domain.
34class XSTileWrap()(implicit p: Parameters) extends LazyModule
35  with HasXSParameter
36  with HasSoCParameter
37{
38  override def shouldBeInlined: Boolean = false
39
40  val tile = LazyModule(new XSTile())
41
42  // interrupts sync
43  val clintIntNode = IntIdentityNode()
44  val debugIntNode = IntIdentityNode()
45  val plicIntNode = IntIdentityNode()
46  val beuIntNode = IntIdentityNode()
47  val nmiIntNode = IntIdentityNode()
48  tile.clint_int_node := IntBuffer(3, cdc = true) := clintIntNode
49  tile.debug_int_node := IntBuffer(3, cdc = true) := debugIntNode
50  tile.plic_int_node :*= IntBuffer(3, cdc = true) :*= plicIntNode
51  tile.nmi_int_node := IntBuffer(3, cdc = true) := nmiIntNode
52  beuIntNode := IntBuffer() := tile.beu_int_source
53  class XSTileWrapImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) {
54    val clock = IO(Input(Clock()))
55    val reset = IO(Input(AsyncReset()))
56    val noc_reset = EnableCHIAsyncBridge.map(_ => IO(Input(AsyncReset())))
57    val soc_reset = IO(Input(AsyncReset()))
58    val io = IO(new Bundle {
59      val hartId = Input(UInt(hartIdLen.W))
60      val msiInfo = Input(ValidIO(new MsiInfoBundle))
61      val reset_vector = Input(UInt(PAddrBits.W))
62      val cpu_halt = Output(Bool())
63      val cpu_crtical_error = Output(Bool())
64      val hartResetReq = Input(Bool())
65      val hartIsInReset = Output(Bool())
66      val traceCoreInterface = new TraceCoreInterface
67      val debugTopDown = new Bundle {
68        val robHeadPaddr = Valid(UInt(PAddrBits.W))
69        val l3MissMatch = Input(Bool())
70      }
71      val chi = EnableCHIAsyncBridge match {
72        case Some(param) => new AsyncPortIO(param)
73        case None => new PortIO
74      }
75      val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None
76      val clintTime = EnableClintAsyncBridge match {
77        case Some(param) => Flipped(new AsyncBundle(UInt(64.W), param))
78        case None => Input(ValidIO(UInt(64.W)))
79      }
80    })
81
82    val reset_sync = withClockAndReset(clock, (reset.asBool || io.hartResetReq).asAsyncReset)(ResetGen())
83    val noc_reset_sync = EnableCHIAsyncBridge.map(_ => withClockAndReset(clock, noc_reset.get)(ResetGen()))
84    val soc_reset_sync = withClockAndReset(clock, soc_reset)(ResetGen())
85
86    // override LazyRawModuleImp's clock and reset
87    childClock := clock
88    childReset := reset_sync
89
90    val imsicAsync = withClockAndReset(clock, reset_sync)(Module(new IMSICAsync()))
91    imsicAsync.i.msiInfo := io.msiInfo
92
93    tile.module.io.hartId := io.hartId
94    tile.module.io.msiInfo := imsicAsync.o.msiInfo
95    tile.module.io.reset_vector := io.reset_vector
96    io.cpu_halt := tile.module.io.cpu_halt
97    io.cpu_crtical_error := tile.module.io.cpu_crtical_error
98    io.hartIsInReset := tile.module.io.hartIsInReset
99    io.traceCoreInterface <> tile.module.io.traceCoreInterface
100    io.debugTopDown <> tile.module.io.debugTopDown
101    tile.module.io.nodeID.foreach(_ := io.nodeID.get)
102
103    // CLINT Async Queue Sink
104    EnableClintAsyncBridge match {
105      case Some(param) =>
106        val sink = withClockAndReset(clock, soc_reset_sync)(Module(new AsyncQueueSink(UInt(64.W), param)))
107        sink.io.async <> io.clintTime
108        sink.io.deq.ready := true.B
109        tile.module.io.clintTime.valid := sink.io.deq.valid
110        tile.module.io.clintTime.bits := sink.io.deq.bits
111      case None =>
112        tile.module.io.clintTime := io.clintTime
113    }
114
115    // CHI Async Queue Source
116    EnableCHIAsyncBridge match {
117      case Some(param) =>
118        val source = withClockAndReset(clock, noc_reset_sync.get)(Module(new CHIAsyncBridgeSource(param)))
119        source.io.enq <> tile.module.io.chi.get
120        io.chi <> source.io.async
121      case None =>
122        require(enableCHI)
123        io.chi <> tile.module.io.chi.get
124    }
125
126    withClockAndReset(clock, reset_sync) {
127      // Modules are reset one by one
128      // reset ----> SYNC --> XSTile
129      val resetChain = Seq(Seq(tile.module))
130      ResetGen(resetChain, reset_sync, !debugOpts.FPGAPlatform)
131    }
132    dontTouch(io.hartId)
133    dontTouch(io.msiInfo)
134  }
135  lazy val module = new XSTileWrapImp(this)
136}
137