xref: /XiangShan/src/main/scala/xiangshan/XSTileWrap.scala (revision 8a020714df826c6ac860308700137855ecd6ba07) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan
18
19import chisel3._
20import chisel3.util._
21import org.chipsalliance.cde.config._
22import freechips.rocketchip.diplomacy._
23import freechips.rocketchip.interrupts._
24import freechips.rocketchip.util._
25import system.HasSoCParameter
26import device.{IMSICAsync, MsiInfoBundle}
27import coupledL2.tl2chi.{PortIO, AsyncPortIO, CHIAsyncBridgeSource}
28import utility.IntBuffer
29
30// This module is used for XSNoCTop for async time domain and divide different
31// voltage domain. Everything in this module should be in the core clock domain
32// and higher voltage domain.
33class XSTileWrap()(implicit p: Parameters) extends LazyModule
34  with HasXSParameter
35  with HasSoCParameter
36{
37  override def shouldBeInlined: Boolean = false
38
39  val tile = LazyModule(new XSTile())
40
41  // interrupts sync
42  val clintIntNode = IntIdentityNode()
43  val debugIntNode = IntIdentityNode()
44  val plicIntNode = IntIdentityNode()
45  tile.clint_int_node := IntBuffer(2) := clintIntNode
46  tile.debug_int_node := IntBuffer(2) := debugIntNode
47  tile.plic_int_node :*= IntBuffer(2) :*= plicIntNode
48  class XSTileWrapImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
49    val chiAsyncBridgeParams = soc.CHIAsyncBridge
50
51    val io = IO(new Bundle {
52      val hartId = Input(UInt(hartIdLen.W))
53      val msiInfo = Input(ValidIO(new MsiInfoBundle))
54      val reset_vector = Input(UInt(PAddrBits.W))
55      val cpu_halt = Output(Bool())
56      val debugTopDown = new Bundle {
57        val robHeadPaddr = Valid(UInt(PAddrBits.W))
58        val l3MissMatch = Input(Bool())
59      }
60      val chi = if (enableCHI) Some(new AsyncPortIO(chiAsyncBridgeParams)) else None
61      val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None
62      val clintTimeAsync = Flipped(new AsyncBundle(UInt(64.W), AsyncQueueParams(1)))
63    })
64
65    val imsicAsync = Module(new IMSICAsync())
66    imsicAsync.i.msiInfo := io.msiInfo
67
68    tile.module.io.hartId := io.hartId
69    tile.module.io.msiInfo := imsicAsync.o.msiInfo
70    tile.module.io.reset_vector := io.reset_vector
71    io.cpu_halt := tile.module.io.cpu_halt
72    io.debugTopDown <> tile.module.io.debugTopDown
73    tile.module.io.nodeID.foreach(_ := io.nodeID.get)
74
75    // CLINT Async Queue Sink
76    val clintTimeAsyncQueueSink = Module(new AsyncQueueSink(UInt(64.W), AsyncQueueParams(1)))
77    clintTimeAsyncQueueSink.io.async <> io.clintTimeAsync
78    clintTimeAsyncQueueSink.io.deq.ready := true.B
79    tile.module.io.clintTime.valid := clintTimeAsyncQueueSink.io.deq.valid
80    tile.module.io.clintTime.bits := clintTimeAsyncQueueSink.io.deq.bits
81
82    // CHI Async Queue Source
83    if (enableCHI) {
84      val chiAsyncBridgeSource = Module(new CHIAsyncBridgeSource(chiAsyncBridgeParams))
85      chiAsyncBridgeSource.io.enq <> tile.module.io.chi.get
86      io.chi.get <> chiAsyncBridgeSource.io.async
87    }
88
89    dontTouch(io.hartId)
90    dontTouch(io.msiInfo)
91  }
92  lazy val module = new XSTileWrapImp(this)
93}
94