1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chisel3._ 20import chisel3.util._ 21import org.chipsalliance.cde.config._ 22import freechips.rocketchip.diplomacy._ 23import freechips.rocketchip.interrupts._ 24import freechips.rocketchip.tilelink._ 25import freechips.rocketchip.util._ 26import system.HasSoCParameter 27import device.{IMSICAsync, MsiInfoBundle} 28import coupledL2.tl2chi.{AsyncPortIO, CHIAsyncBridgeSource, PortIO} 29import utility.sram.SramBroadcastBundle 30import utility.{DFTResetSignals, IntBuffer, ResetGen} 31import xiangshan.backend.trace.TraceCoreInterface 32 33// This module is used for XSNoCTop for async time domain and divide different 34// voltage domain. Everything in this module should be in the core clock domain 35// and higher voltage domain. 36class XSTileWrap()(implicit p: Parameters) extends LazyModule 37 with HasXSParameter 38 with HasSoCParameter 39{ 40 override def shouldBeInlined: Boolean = false 41 42 val tile = LazyModule(new XSTile()) 43 44 // interrupts sync 45 val clintIntNode = IntIdentityNode() 46 val debugIntNode = IntIdentityNode() 47 val plicIntNode = IntIdentityNode() 48 val beuIntNode = IntIdentityNode() 49 val nmiIntNode = IntIdentityNode() 50 tile.clint_int_node := IntBuffer(3, cdc = true) := clintIntNode 51 tile.debug_int_node := IntBuffer(3, cdc = true) := debugIntNode 52 tile.plic_int_node :*= IntBuffer(3, cdc = true) :*= plicIntNode 53 tile.nmi_int_node := IntBuffer(3, cdc = true) := nmiIntNode 54 beuIntNode := IntBuffer() := tile.beu_int_source 55 56 // seperate DebugModule bus 57 val EnableDMAsync = EnableDMAsyncBridge.isDefined 58 println(s"SeperateDMBus = $SeperateDMBus") 59 println(s"EnableDMAsync = $EnableDMAsync") 60 // asynchronous bridge source node 61 val dmAsyncSourceOpt = Option.when(SeperateDMBus && EnableDMAsync)(LazyModule(new TLAsyncCrossingSource())) 62 dmAsyncSourceOpt.foreach(_.node := tile.sep_dm_opt.get) 63 // synchronous source node 64 val dmSyncSourceOpt = Option.when(SeperateDMBus && !EnableDMAsync)(TLTempNode()) 65 dmSyncSourceOpt.foreach(_ := tile.sep_dm_opt.get) 66 67 class XSTileWrapImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) { 68 val clock = IO(Input(Clock())) 69 val reset = IO(Input(AsyncReset())) 70 val noc_reset = EnableCHIAsyncBridge.map(_ => IO(Input(AsyncReset()))) 71 val soc_reset = IO(Input(AsyncReset())) 72 val io = IO(new Bundle { 73 val hartId = Input(UInt(hartIdLen.W)) 74 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 75 val reset_vector = Input(UInt(PAddrBits.W)) 76 val cpu_halt = Output(Bool()) 77 val cpu_crtical_error = Output(Bool()) 78 val hartResetReq = Input(Bool()) 79 val hartIsInReset = Output(Bool()) 80 val traceCoreInterface = new TraceCoreInterface 81 val debugTopDown = new Bundle { 82 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 83 val l3MissMatch = Input(Bool()) 84 } 85 val l3Miss = Input(Bool()) 86 val chi = EnableCHIAsyncBridge match { 87 case Some(param) => new AsyncPortIO(param) 88 case None => new PortIO 89 } 90 val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None 91 val clintTime = EnableClintAsyncBridge match { 92 case Some(param) => Flipped(new AsyncBundle(UInt(64.W), param)) 93 case None => Input(ValidIO(UInt(64.W))) 94 } 95 val dft = if(hasMbist) Some(Input(new SramBroadcastBundle)) else None 96 val dft_reset = if(hasMbist) Some(Input(new DFTResetSignals())) else None 97 val l2_flush_en = Option.when(EnablePowerDown) (Output(Bool())) 98 val l2_flush_done = Option.when(EnablePowerDown) (Output(Bool())) 99 val pwrdown_req_n = Option.when(EnablePowerDown) (Input (Bool())) 100 val pwrdown_ack_n = Option.when(EnablePowerDown) (Output (Bool())) 101 val iso_en = Option.when(EnablePowerDown) (Input (Bool())) 102 }) 103 104 val reset_sync = withClockAndReset(clock, (reset.asBool || io.hartResetReq).asAsyncReset)(ResetGen(2, io.dft_reset)) 105 val noc_reset_sync = EnableCHIAsyncBridge.map(_ => withClockAndReset(clock, noc_reset.get)(ResetGen(2, io.dft_reset))) 106 val soc_reset_sync = withClockAndReset(clock, soc_reset)(ResetGen(2, io.dft_reset)) 107 108 // override LazyRawModuleImp's clock and reset 109 childClock := clock 110 childReset := reset_sync 111 112 val imsicAsync = withClockAndReset(clock, reset_sync)(Module(new IMSICAsync())) 113 imsicAsync.i.msiInfo := io.msiInfo 114 115 tile.module.io.hartId := io.hartId 116 tile.module.io.msiInfo := imsicAsync.o.msiInfo 117 tile.module.io.reset_vector := io.reset_vector 118 tile.module.io.dft.zip(io.dft).foreach({case(a, b) => a := b}) 119 tile.module.io.dft_reset.zip(io.dft_reset).foreach({case(a, b) => a := b}) 120 io.cpu_halt := tile.module.io.cpu_halt 121 io.cpu_crtical_error := tile.module.io.cpu_crtical_error 122 io.hartIsInReset := tile.module.io.hartIsInReset 123 io.traceCoreInterface <> tile.module.io.traceCoreInterface 124 io.debugTopDown <> tile.module.io.debugTopDown 125 tile.module.io.l3Miss := io.l3Miss 126 tile.module.io.nodeID.foreach(_ := io.nodeID.get) 127 io.l2_flush_en.foreach { _ := tile.module.io.l2_flush_en.getOrElse(false.B) } 128 io.l2_flush_done.foreach { _ := tile.module.io.l2_flush_done.getOrElse(false.B) } 129 io.pwrdown_ack_n.foreach { _ := true.B } 130 131 // CLINT Async Queue Sink 132 EnableClintAsyncBridge match { 133 case Some(param) => 134 val sink = withClockAndReset(clock, soc_reset_sync)(Module(new AsyncQueueSink(UInt(64.W), param))) 135 sink.io.async <> io.clintTime 136 sink.io.deq.ready := true.B 137 tile.module.io.clintTime.valid := sink.io.deq.valid 138 tile.module.io.clintTime.bits := sink.io.deq.bits 139 case None => 140 tile.module.io.clintTime := io.clintTime 141 } 142 143 // CHI Async Queue Source 144 EnableCHIAsyncBridge match { 145 case Some(param) => 146 val source = withClockAndReset(clock, noc_reset_sync.get)(Module(new CHIAsyncBridgeSource(param))) 147 source.io.enq <> tile.module.io.chi.get 148 io.chi <> source.io.async 149 case None => 150 require(enableCHI) 151 io.chi <> tile.module.io.chi.get 152 } 153 154 // Seperate DebugModule TL Async Queue Source 155 if (SeperateDMBus && EnableDMAsync) { 156 dmAsyncSourceOpt.get.module.clock := clock 157 dmAsyncSourceOpt.get.module.reset := soc_reset_sync 158 } 159 160 withClockAndReset(clock, reset_sync) { 161 // Modules are reset one by one 162 // reset ----> SYNC --> XSTile 163 val resetChain = Seq(Seq(tile.module)) 164 ResetGen(resetChain, reset_sync, !debugOpts.FPGAPlatform, io.dft_reset) 165 } 166 dontTouch(io.hartId) 167 dontTouch(io.msiInfo) 168 } 169 lazy val module = new XSTileWrapImp(this) 170} 171