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Searched refs:dcc_offset (Results 1 – 9 of 9) sorted by relevance

/aosp_15_r20/external/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_clear.c431 uint64_t dcc_offset = tex->surface.meta_offset; in vi_dcc_get_clear_info() local
447 dcc_offset += tex->surface.u.gfx9.meta_levels[level].offset; in vi_dcc_get_clear_info()
489 dcc_offset += tex->surface.u.legacy.color.dcc_level[level].dcc_offset; in vi_dcc_get_clear_info()
493 si_init_buffer_clear(out, dcc_buffer, dcc_offset, clear_size, clear_value); in vi_dcc_get_clear_info()
H A Dsi_texture.c947 … i, i < tex->surface.num_meta_levels, tex->surface.u.legacy.color.dcc_level[i].dcc_offset, in si_print_texture_info()
1250 size = tex->surface.u.legacy.color.dcc_level[i].dcc_offset + in si_texture_create_object()
/aosp_15_r20/external/mesa3d/src/amd/vulkan/meta/
H A Dradv_meta_clear.c1167 uint64_t dcc_offset = image->planes[0].surface.meta_offset; in radv_clear_dcc() local
1173 dcc_offset += image->planes[0].surface.meta_slice_size * range->baseArrayLayer + in radv_clear_dcc()
1189 …dcc_offset += dcc_level->dcc_offset + dcc_level->dcc_slice_fast_clear_size * range->baseArrayLayer; in radv_clear_dcc()
1197 …adv_fill_buffer(cmd_buffer, image, image->bindings[0].bo, radv_image_get_va(image, 0) + dcc_offset, in radv_clear_dcc()
/aosp_15_r20/external/mesa3d/src/amd/common/
H A Dac_surface.c911 dcc_level->dcc_offset = 0; in gfx6_compute_level()
926 dcc_level->dcc_offset = surf->meta_size; in gfx6_compute_level()
928 surf->meta_size = dcc_level->dcc_offset + AddrDccOut->dccRamSize; in gfx6_compute_level()
3551 uint64_t dcc_offset = 0; in ac_surface_compute_bo_metadata() local
3554 dcc_offset = surf->display_dcc_offset ? surf->display_dcc_offset : surf->meta_offset; in ac_surface_compute_bo_metadata()
3555 assert((dcc_offset >> 8) != 0 && (dcc_offset >> 8) < (1 << 24)); in ac_surface_compute_bo_metadata()
3559 *tiling_flags |= AMDGPU_TILING_SET(DCC_OFFSET_256B, dcc_offset >> 8); in ac_surface_compute_bo_metadata()
H A Dac_surface.h97 uint32_t dcc_offset; /* relative offset within DCC mip tree */ member
H A Dac_descriptors.c594 meta_va += surf->u.legacy.color.dcc_level[state->gfx6.base_level].dcc_offset; in ac_set_mutable_tex_desc_fields()
1397 cb->cb_dcc_base += surf->u.legacy.color.dcc_level[state->base_level].dcc_offset >> 8; in ac_set_mutable_cb_surface_fields()
/aosp_15_r20/external/mesa3d/src/amd/vulkan/
H A Dradv_image.c786 uint64_t dcc_offset = in radv_init_metadata() local
789 metadata->u.gfx9.dcc_offset_256b = dcc_offset >> 8; in radv_init_metadata()
H A Dradv_cmd_buffer.c12566 size = dcc_level->dcc_offset + dcc_fast_clear_size; in radv_init_dcc()
/aosp_15_r20/external/mesa3d/docs/relnotes/
H A D20.2.0.rst3235 - radeonsi: use vi_dcc_enabled instead of using tex->surface.dcc_offset directly