Searched refs:verilog (Results 1 – 6 of 6) sorted by relevance
87 * 运行 `make verilog` 以生成 verilog 代码。输出文件为 `build/XSTop.v`。102 * 安装开源 verilog 仿真器 [Verilator](https://verilator.org/guide/latest/)。
2 verilog-decode:
91 * Run `make verilog` to generate verilog code. The output file is `build/XSTop.v`.
52 names.map { name => { (verilog: VerilogAXI4Record, chisel: AXI4Bundle) => {58 verilog.elements(name) -> channel.elements.applyOrElse(signal,
51 names.map { name => { (verilog: VerilogAXI4LiteRecord, chisel: AXI4LiteBundle) => {57 verilog.elements(name) -> channel.elements.applyOrElse(signal,
415 val verilog = constant467 FileRegisters.writeOutputFile("./build", "XSDiffTopChecker.sv", verilog)