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Searched refs:splitStoreResp (Results 1 – 2 of 2) sorted by relevance

/XiangShan/src/main/scala/xiangshan/mem/lsqueue/
H A DStoreMisalignBuffer.scala102 val splitStoreResp = Flipped(Valid(new SqWriteBundle)) constant
204 val splitStoreResp = RegInit(VecInit(List.fill(maxSplitNum)(0.U.asTypeOf(new SqWriteBundle)))) constant
219 val hasException = io.splitStoreResp.bits.vecActive && !io.splitStoreResp.bits.need_rep &&
220 …ExceptionNO.selectByFu(io.splitStoreResp.bits.uop.exceptionVec, StaCfg).asUInt.orR || TriggerActio…
221 …val isUncache = (io.splitStoreResp.bits.mmio || io.splitStoreResp.bits.nc) && !io.splitStoreResp.b…
225 …io.sqControl.toStoreQueue.paddr := Cat(splitStoreResp(1).paddr(splitStoreResp(1).paddr.getWidth - …
258 when (io.splitStoreResp.valid) {
266 globalMMIO := io.splitStoreResp.bits.mmio
267 globalNC := io.splitStoreResp.bits.nc
268 } .elsewhen(io.splitStoreResp.bits.need_rep || (unSentStores & (~clearOh).asUInt).orR) {
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/XiangShan/src/main/scala/xiangshan/mem/
H A DMemBlock.scala1261 stu.io.misalign_stout <> storeMisalignBuffer.io.splitStoreResp