Home
last modified time | relevance | path

Searched refs:hptw_req_arb (Results 1 – 2 of 2) sorted by relevance

/XiangShan/src/main/scala/xiangshan/cache/mmu/
H A DL2TLB.scala129 val hptw_req_arb = Module(new Arbiter(new Bundle { constant
160 hptw_req_arb.io.in(InHptwArbPTWPort).valid := ptw.io.hptw.req.valid
161 hptw_req_arb.io.in(InHptwArbPTWPort).bits.gvpn := ptw.io.hptw.req.bits.gvpn
162 hptw_req_arb.io.in(InHptwArbPTWPort).bits.id := ptw.io.hptw.req.bits.id
163 hptw_req_arb.io.in(InHptwArbPTWPort).bits.source := ptw.io.hptw.req.bits.source
164 ptw.io.hptw.req.ready := hptw_req_arb.io.in(InHptwArbPTWPort).ready
166 hptw_req_arb.io.in(InHptwArbLLPTWPort).valid := llptw.io.hptw.req.valid
167 hptw_req_arb.io.in(InHptwArbLLPTWPort).bits.gvpn := llptw.io.hptw.req.bits.gvpn
168 hptw_req_arb.io.in(InHptwArbLLPTWPort).bits.id := llptw.io.hptw.req.bits.id
169 hptw_req_arb.io.in(InHptwArbLLPTWPort).bits.source := llptw.io.hptw.req.bits.source
[all …]
H A DPageTableWalker.scala1026 val hptw_req_arb = Module(new Arbiter(new Bundle{ constant
1032 hptw_req_arb.io.in(0).valid := hyper_arb1.io.out.valid
1033 hptw_req_arb.io.in(0).bits.source := hyper_arb1.io.out.bits.req_info.source
1034 hptw_req_arb.io.in(0).bits.ppn := hyper_arb1.io.out.bits.ppn
1035 hptw_req_arb.io.in(0).bits.id := hyper_arb1.io.chosen
1036 hyper_arb1.io.out.ready := hptw_req_arb.io.in(0).ready
1038 hptw_req_arb.io.in(1).valid := hyper_arb2.io.out.valid
1039 hptw_req_arb.io.in(1).bits.source := hyper_arb2.io.out.bits.req_info.source
1040 hptw_req_arb.io.in(1).bits.ppn := hyper_arb2.io.out.bits.ppn
1041 hptw_req_arb.io.in(1).bits.id := hyper_arb2.io.chosen
[all …]