| /XiangShan/scripts/ |
| H A D | vlsi_mem_gen | 61 def generate(self, blackbox): member in VerilogModuleGenerator
85 def generate(self, mem): member in Reshaper
124 def generate(self, mem): member in Spliter
222 def generate(self, blackbox): member in SRAM
324 return mem.generate(blackbox)
362 reshaper.generate(self.mem)
386 return mem.generate(blackbox)
388 def generate(self, blackbox, itself_only=False): member in SRAM_TSMC28
392 return self.mem.generate("")
395 return super().generate(" ")
[all …]
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| H A D | xiangshan.py | 293 (args.generate, lambda _ : self.generate_verilog()),
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| /XiangShan/src/main/scala/xiangshan/frontend/icache/ |
| H A D | ICacheBundle.scala | 38 def generate(tag: UInt, idx: UInt, waymask: UInt, bankIdx: Bool, poison: Bool): Unit = { method
59 def generate(data: UInt, idx: UInt, waymask: UInt, bankIdx: Bool, poison: Bool): Unit = { method
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| H A D | ICacheCtrlUnit.scala | 169 io.metaWrite.bits.generate(
178 io.dataWrite.bits.generate(
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| H A D | ICacheMissUnit.scala | 393 io.meta_write.bits.generate(
400 io.data_write.bits.generate(
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| /XiangShan/scripts/top-down/ |
| H A D | README.md | 9 usage: generate top-down results
47 usage: generate top-down results
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| /XiangShan/src/main/scala/xiangshan/backend/decode/ |
| H A D | VecDecoder.scala | 17 def generate() : List[BitPat] method
19 …p::xWen::fWen::vWen::mWen::vxsatWen::xsTrap::noSpec::blockBack::flushPipe::selImm::Nil = generate()
23 …p::xWen::fWen::vWen::mWen::vxsatWen::xsTrap::noSpec::blockBack::flushPipe::selImm::Nil = generate()
39 def generate() : List[BitPat] = { method
41 …Wen = F, vWen = vWen, mWen = mWen, xsTrap = F, noSpec = F, blockBack = F, flushPipe = F).generate()
56 def generate() : List[BitPat] = { method
58 …Wen = F, vWen = vWen, mWen = mWen, xsTrap = F, noSpec = F, blockBack = F, flushPipe = F).generate()
74 def generate() : List[BitPat] = { method
76 …Wen = F, vWen = vWen, mWen = mWen, xsTrap = F, noSpec = F, blockBack = F, flushPipe = F).generate()
92 def generate() : List[BitPat] = { method
[all …]
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| H A D | DecodeUnit.scala | 64 final def table: Array[(BitPat, List[BitPat])] = decodeArray.map(x => (x._1, x._2.generate()))
91 def generate() : List[BitPat] method
108 def generate() : List[BitPat] = { method
127 def generate() : List[BitPat] = { method
128 …SplitType, xWen, fWen, vWen, mWen, xsTrap, noSpec, blockBack, flushPipe, canRobCompress).generate()
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| /XiangShan/src/main/scala/device/ |
| H A D | AXI4Timer.scala | 58 RegMap.generate(mapping, getOffset(raddr), in.r.bits.data,
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| H A D | AXI4UART.scala | 52 RegMap.generate(mapping, raddr(3,0), in.r.bits.data,
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| H A D | AXI4DummySD.scala | 118 RegMap.generate(mapping, getOffset(raddr), rdata,
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| H A D | AXI4Plic.scala | 175 RegMap.generate(mapping, getOffset(raddr), rdata,
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| H A D | AXI4VGA.scala | 88 RegMap.generate(mapping, raddr(3, 0), in.r.bits.data,
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| /XiangShan/src/main/scala/xiangshan/mem/vector/ |
| H A D | VSplit.scala | 48 * decode and generate AlignedType, uop mask, preIsSplit
180 * generate UopOffset
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| /XiangShan/ |
| H A D | README.md | 91 * Run `make verilog` to generate verilog code. The output file is `build/XSTop.v`.
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| /XiangShan/src/main/scala/xiangshan/backend/fu/ |
| H A D | PMP.scala | 363 MaskedRegMap.generate(mapping, w.bits.addr, rdata, w.valid, w.bits.data)
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