Bump rocket-chip (#2353)

chore: remove deprecated brackets, APIs, etc. (#2321)

Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

use ExtModule instead of Chisel3.BlackBox. (#988)

Bump chisel to 3.5 (#974)

* bump chisel to 3.5

* Remove deprecated 'toBool' && disable tl monitor

* Update RocketChip / Re-enable TLMonitor

* Makefile: remove '--infer-rw'

misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.

AXI4SlaveModule: use Seq[AddressSet] instead of AddressSet
to allow more flexible address range configuration.
With only one AddressSet, we can not even represent
very simple address ranges like [2G,

AXI4SlaveModule: use Seq[AddressSet] instead of AddressSet
to allow more flexible address range configuration.
With only one AddressSet, we can not even represent
very simple address ranges like [2G, 32G).

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Add 'memByte' arg to AXIRAM

Rewrite AXI4 VGA

device,AXI4VGA: support hdmi signals

device,AXI4VGA: add FBHelper for emu

device,AXI4VGA: rewrite VGACtrl with RegMap

device,AXI4VGA: change fb to AXI4Lite, and connect vga at SimMMIO

device,AXI4VGA: fix vga bug, but still not perfect

* Due to the modification of AXI4Slave, now AXI4RAM has 2 cycle of
latency.
* The display is still not perfect. Some vertical lines are still wro

device,AXI4VGA: fix vga bug, but still not perfect

* Due to the modification of AXI4Slave, now AXI4RAM has 2 cycle of
latency.
* The display is still not perfect. Some vertical lines are still wrong.
* We should modify the vga code to be independent of the behavior of
AXI4RAM.

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device,AXI4VGA: use 2 bit id for frame buffer

device,AXI4VGA: use AXI4 for frame buffer to support burst write

device,VGA: rename to AXI4VGA