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Searched hist:"45 f43e6e5f88874a7573ff096d1e5c2855bd16c7" (Results 1 – 16 of 16) sorted by relevance

/XiangShan/src/main/scala/utils/
H A DTrigger.scaladiff 45f43e6e5f88874a7573ff096d1e5c2855bd16c7 Fri Jan 19 08:05:34 CET 2024 Tang Haojin <[email protected]> chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/
H A DDatamoduleResultBuffer.scaladiff 45f43e6e5f88874a7573ff096d1e5c2855bd16c7 Fri Jan 19 08:05:34 CET 2024 Tang Haojin <[email protected]> chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`
/XiangShan/src/main/scala/xiangshan/backend/fu/
H A DSRT16Divider.scaladiff 45f43e6e5f88874a7573ff096d1e5c2855bd16c7 Fri Jan 19 08:05:34 CET 2024 Tang Haojin <[email protected]> chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`
H A DSRT4Divider.scaladiff 45f43e6e5f88874a7573ff096d1e5c2855bd16c7 Fri Jan 19 08:05:34 CET 2024 Tang Haojin <[email protected]> chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`
H A DMultiplier.scaladiff 45f43e6e5f88874a7573ff096d1e5c2855bd16c7 Fri Jan 19 08:05:34 CET 2024 Tang Haojin <[email protected]> chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`
H A DCSR.scaladiff 45f43e6e5f88874a7573ff096d1e5c2855bd16c7 Fri Jan 19 08:05:34 CET 2024 Tang Haojin <[email protected]> chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`
/XiangShan/src/main/scala/xiangshan/mem/prefetch/
H A DL1PrefetchComponent.scaladiff 45f43e6e5f88874a7573ff096d1e5c2855bd16c7 Fri Jan 19 08:05:34 CET 2024 Tang Haojin <[email protected]> chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`
/XiangShan/src/main/scala/xiangshan/cache/mmu/
H A DTLBStorage.scaladiff 45f43e6e5f88874a7573ff096d1e5c2855bd16c7 Fri Jan 19 08:05:34 CET 2024 Tang Haojin <[email protected]> chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`
H A DL2TLB.scaladiff 45f43e6e5f88874a7573ff096d1e5c2855bd16c7 Fri Jan 19 08:05:34 CET 2024 Tang Haojin <[email protected]> chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`
H A DMMUBundle.scaladiff 45f43e6e5f88874a7573ff096d1e5c2855bd16c7 Fri Jan 19 08:05:34 CET 2024 Tang Haojin <[email protected]> chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`
/XiangShan/.github/workflows/
H A Demu.ymldiff 45f43e6e5f88874a7573ff096d1e5c2855bd16c7 Fri Jan 19 08:05:34 CET 2024 Tang Haojin <[email protected]> chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`
/XiangShan/
H A Dbuild.scdiff 45f43e6e5f88874a7573ff096d1e5c2855bd16c7 Fri Jan 19 08:05:34 CET 2024 Tang Haojin <[email protected]> chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`
H A DMakefilediff 45f43e6e5f88874a7573ff096d1e5c2855bd16c7 Fri Jan 19 08:05:34 CET 2024 Tang Haojin <[email protected]> chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`
/XiangShan/scripts/
H A Dxiangshan.pydiff 45f43e6e5f88874a7573ff096d1e5c2855bd16c7 Fri Jan 19 08:05:34 CET 2024 Tang Haojin <[email protected]> chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/
H A DMainPipe.scaladiff 45f43e6e5f88874a7573ff096d1e5c2855bd16c7 Fri Jan 19 08:05:34 CET 2024 Tang Haojin <[email protected]> chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`
H A DMissQueue.scaladiff 45f43e6e5f88874a7573ff096d1e5c2855bd16c7 Fri Jan 19 08:05:34 CET 2024 Tang Haojin <[email protected]> chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`