| /nrf52832-nimble/rt-thread/libcpu/mips/common/ |
| H A D | mips_cache.h | 33 * Cache Operations available on all MIPS processors with R4000-style caches
128 "cache %0, %1\n" \
137 " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \
138 " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \
139 " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \
140 " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \
141 " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \
142 " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \
143 " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \
144 " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \
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| /nrf52832-nimble/rt-thread/libcpu/c-sky/common/ |
| H A D | csi_core.h | 111 /* ########################## Cache functions #################################### */
114 \brief Enable I-Cache
115 \details Turns on I-Cache
120 \brief Disable I-Cache
121 \details Turns off I-Cache
126 \brief Invalidate I-Cache
127 \details Invalidates I-Cache
132 \brief Enable D-Cache
133 \details Turns on D-Cache
134 \note I-Cache also turns on.
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| /nrf52832-nimble/rt-thread/libcpu/arm/armv6/ |
| H A D | mmu.h | 102 …(SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT) /* Read/Write/executable, cache, write back */
103 …CT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT) /* Read/Write/executable, cache, write through */
104 …(SECT_AP_RW|PGD_DOMAIN(0)|PGD_TYPE_SECT) /* Read/Write/executable without cache and write buffer */
105 #define SECT_RWX_FAULT (SECT_AP_RW|PGD_DOMAIN(1)|PGD_TYPE_SECT) /* Read/Write without cache and w…
107 …SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_SECT_XN) /* Read/Write, cache, write back */
108 …T_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_SECT_XN) /* Read/Write, cache, write through */
109 …SECT_AP_RW|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_SECT_XN) /* Read/Write without cache and write buffer */
110 …SECT_AP_RW|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_SECT_XN) /* Read/Write without cache and write buffer */
113 … (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT) /* Read Only/executable, cache, write back */
114 …ECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT) /* Read Only/executable, cache, write through */
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| H A D | cpuport.c | 93 * enable I-Cache
102 * disable I-Cache
111 * return the status of I-Cache
120 * enable D-Cache
129 * disable D-Cache
138 * return the status of D-Cache
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| /nrf52832-nimble/rt-thread/libcpu/mips/loongson_1c/ |
| H A D | cache_gcc.S | 20 #include "cache.h"
92 cache Index_Store_Tag_D, 0x0(v0) # 1 way
94 cache Index_Store_Tag_D, 0x1(v0) # 2 way
95 cache Index_Store_Tag_D, 0x2(v0) # 4 way
96 cache Index_Store_Tag_D, 0x3(v0)
107 cache Index_Invalidate_I, 0x0(v0) # 1 way
109 cache Index_Invalidate_I, 0x1(v0) # 2 way
110 cache Index_Invalidate_I, 0x2(v0)
111 cache Index_Invalidate_I, 0x3(v0) # 4 way
122 cache Index_Writeback_Inv_D, 0x0(v0) #1 way
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| H A D | start_gcc.S | 19 #include "cache.h"
64 /* disable cache */
68 mtc0 t0, CP0_CONFIG # Set CPU to disable cache.
263 * 冷启动，则需要初始化内存，cache，加载代码到内存等
356 /**************************************CACHE*****************************/
358 #define CF_7_SE (1 << 3) /* Secondary cache enable */
359 #define CF_7_SC (1 << 31) /* Secondary cache not present */
360 #define CF_7_TE (1 << 12) /* Tertiary cache enable */
361 #define CF_7_TC (1 << 17) /* Tertiary cache not present */
362 #define CF_7_TS (3 << 20) /* Tertiary cache size */
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| H A D | cache.c | 2 * File : cache.c
162 //with cache disabled
180 /* 1. identify cpu and probe cache */ in rt_hw_cache_init()
193 * 3. invalidate instruction cache; in rt_hw_cache_init()
202 * 4. invalidate data cache; in rt_hw_cache_init()
226 /* enable cache */ in rt_hw_cache_init()
228 rt_kprintf("enable cpu cache done\n"); in rt_hw_cache_init()
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| /nrf52832-nimble/rt-thread/libcpu/mips/loongson_1b/ |
| H A D | cache_gcc.S | 19 #include "cache.h"
91 cache Index_Store_Tag_D, 0x0(v0) # 1 way
93 cache Index_Store_Tag_D, 0x1(v0) # 2 way
94 cache Index_Store_Tag_D, 0x2(v0) # 4 way
95 cache Index_Store_Tag_D, 0x3(v0)
106 cache Index_Invalidate_I, 0x0(v0) # 1 way
108 cache Index_Invalidate_I, 0x1(v0) # 2 way
109 cache Index_Invalidate_I, 0x2(v0)
110 cache Index_Invalidate_I, 0x3(v0) # 4 way
121 cache Index_Writeback_Inv_D, 0x0(v0) #1 way
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| H A D | cache.c | 2 * File : cache.c
161 //with cache disabled
179 /* 1. identify cpu and probe cache */ in rt_hw_cache_init()
192 * 3. invalidate instruction cache; in rt_hw_cache_init()
201 * 4. invalidate data cache; in rt_hw_cache_init()
225 /* enable cache */ in rt_hw_cache_init()
227 rt_kprintf("enable cpu cache done\n"); in rt_hw_cache_init()
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| /nrf52832-nimble/rt-thread/libcpu/arm/dm36x/ |
| H A D | mmu.h | 101 … (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write, cache, write back */
102 …SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write, cache, write through */
103 … (SECT_AP_RW|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write without cache and write buffer */
104 … (SECT_AP_RW|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write without cache and write buffer */
106 … (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_BIT4) /* Read Only, cache, write back */
107 …(SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_BIT4) /* Read Only, cache, write through */
108 … (SECT_AP_RO|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_BIT4) /* Read Only without cache and write buffer */
109 … (SECT_AP_RO|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_BIT4) /* Read Only without cache and write buffer */
124 #define PAGE_RW_CB (PAGE_AP_RW|PAGE_CB|PTE_TYPE_SMALL) /* Read/Write, cache, write back */
125 #define PAGE_RW_CNB (PAGE_AP_RW|PAGE_CNB|PTE_TYPE_SMALL) /* Read/Write, cache, write through */
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| H A D | cpuport.c | 91 * enable I-Cache
100 * disable I-Cache
109 * return the status of I-Cache
118 * enable D-Cache
127 * disable D-Cache
136 * return the status of D-Cache
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| /nrf52832-nimble/rt-thread/libcpu/ppc/ppc405/ |
| H A D | cache_gcc.S | 6 * Flush instruction cache.
15 * Write any modified data cache blocks out to memory
16 * and invalidate the corresponding instruction cache blocks.
43 * Write any modified data cache blocks out to memory.
44 * Does not invalidate the corresponding cache lines (especially for
45 * any corresponding instruction cache).
66 * Write any modified data cache blocks out to memory and invalidate them.
67 * Does not invalidate the corresponding instruction cache blocks.
88 * Like above, but invalidate the D-cache. This is used by the 8xx
89 * to invalidate the cache so the PPC core doesn't get stale data
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| /nrf52832-nimble/rt-thread/libcpu/arm/cortex-r4/ |
| H A D | cpu.c | 55 __asm(" ORR r1, r1, #0x1 <<12 ; instruction cache enable"); in rt_hw_cpu_icache_enable()
56 __asm(" MCR p15, #0, r0, c7, c5, #0 ; Invalidate entire instruction cache, r0 is ignored"); in rt_hw_cpu_icache_enable()
57 __asm(" MCR p15, #0, r1, c1, c0, #0 ; enabled instruction cache"); in rt_hw_cpu_icache_enable()
64 __asm(" BIC r1, r1, #0x1 <<12 ; instruction cache enable"); in rt_hw_cpu_icache_disable()
65 __asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled instruction cache"); in rt_hw_cpu_icache_disable()
74 __asm(" MCR p15, #0, r0, c15, c5, #0 ; Invalidate entire data cache"); in rt_hw_cpu_dcache_enable()
75 __asm(" MCR p15, #0, R1, c1, c0, #0 ; enabled data cache"); in rt_hw_cpu_dcache_enable()
80 /* FIXME: Clean entire data cache. This routine depends on the data cache in rt_hw_cpu_dcache_disable()
81 * size. It can be omitted if it is known that the data cache has no dirty in rt_hw_cpu_dcache_disable()
86 __asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled data cache"); in rt_hw_cpu_dcache_disable()
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| /nrf52832-nimble/rt-thread/components/dfs/filesystems/uffs/src/uffs/ |
| H A D | uffs_blockinfo.c | 35 * \brief block information cache system manipulations
51 * \brief before block info cache is enable,
55 * \param[in] maxCachedBlocks maximum cache buffers to be allocated
70 "block info cache has been inited already, " in uffs_BlockInfoInitCache()
89 "Block cache buffer require %d but only %d available.", in uffs_BlockInfoInitCache()
94 uffs_Perror(UFFS_MSG_NOISY, "alloc info cache %d bytes.", size); in uffs_BlockInfoInitCache()
145 * \brief release all allocated memory of block info cache,
157 "There have refed block info cache, release cache fail."); in uffs_BlockInfoReleaseCache()
263 * \brief find a block cache with given block number
266 * \return found block cache
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| /nrf52832-nimble/rt-thread/libcpu/ppc/ppc405/include/asm/ |
| H A D | processor.h | 21 #define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
104 #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
181 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
185 #define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */
186 #define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */
189 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
200 #define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */
201 #define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */
202 #define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */
203 #define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */
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| /nrf52832-nimble/rt-thread/libcpu/arm/s3c44b0/ |
| H A D | cpu.c | 20 * This function will enable I-Cache of CPU
35 * Init cache in rt_hw_cpu_icache_enable()
51 * This function will disable I-Cache of CPU
64 * this function will get the status of I-Cache
73 * this function will enable D-Cache of CPU
82 * this function will disable D-Cache of CPU
91 * this function will get the status of D-Cache
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| /nrf52832-nimble/rt-thread/libcpu/mips/xburst/ |
| H A D | start_gcc.S | 33 /* init caches, assumes a 4way * 128set * 32byte I/D cache */
36 li t0, 3 /* enable cache for kseg0 accesses */
39 ori t1, t0, 0x4000 /* 16kB cache */
42 cache 0x8, 0(t0) /* index store icache tag */
43 cache 0x9, 0(t0) /* index store dcache tag */
45 addiu t0, t0, 0x20 /* 32 bytes per cache line */
115 /* 0x100 - Cache error handler */
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| H A D | cache_gcc.S | 19 move t0, a0 // cache total size
20 move t1, a1 // cache line size
25 cache 8, 0(t2) // icache_index_store_tag
26 cache 9, 0(t2) // dcache_index_store_tag
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| /nrf52832-nimble/rt-thread/components/dfs/filesystems/uffs/src/inc/uffs/ |
| H A D | uffs_blockinfo.h | 60 UFFS use a cache system to speed up block info access.
81 /** load page spare to block info cache */
84 /** find block info cache */
87 /** get block info cache, load it on demand */
90 /** put info cache back to pool, should be called with #uffs_BlockInfoGet in pairs. */
93 /** explicitly expire a block info cache */
96 /** no one hold any block info cache ? safe to release block info caches */
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| /nrf52832-nimble/rt-thread/libcpu/arm/am335x/ |
| H A D | cpu.c | 94 * enable I-Cache
103 * disable I-Cache
112 * return the status of I-Cache
121 * enable D-Cache
130 * disable D-Cache
139 * return the status of D-Cache
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| /nrf52832-nimble/rt-thread/libcpu/arm/s3c24x0/ |
| H A D | cpu.c | 94 * enable I-Cache
103 * disable I-Cache
112 * return the status of I-Cache
121 * enable D-Cache
130 * disable D-Cache
139 * return the status of D-Cache
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| /nrf52832-nimble/rt-thread/libcpu/arm/sep4020/ |
| H A D | cpu.c | 98 * enable I-Cache in cp15_rd()
107 * disable I-Cache in cp15_rd()
116 * return the status of I-Cache in cp15_rd()
125 * enable D-Cache in cp15_rd()
134 * disable D-Cache in cp15_rd()
143 * return the status of D-Cache in cp15_rd()
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| /nrf52832-nimble/rt-thread/libcpu/arm/arm926/ |
| H A D | cpuport.c | 92 * enable I-Cache
101 * disable I-Cache
110 * return the status of I-Cache
119 * enable D-Cache
128 * disable D-Cache
137 * return the status of D-Cache
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| /nrf52832-nimble/rt-thread/libcpu/unicore32/sep6200/ |
| H A D | cpu.c | 182 * enable I-Cache
191 * disable I-Cache
200 * return the status of I-Cache
209 * enable D-Cache
218 * disable D-Cache
227 * return the status of D-Cache
238 "movc p0.c5, ip, #28\n" /*Cache invalidate all*/ in sep6200_reset()
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| /nrf52832-nimble/rt-thread/tools/kconfig-frontends/ |
| H A D | INSTALL | 33 It can also use an optional file (typically called `config.cache'
34 and enabled with `--cache-file=config.cache' or simply `-C') that saves
37 cache files.
42 be considered for the next release. If you are using the cache, and at
43 some point `config.cache' contains results you don't want to keep, you
333 `--cache-file=FILE'
334 Enable the cache: use and save the results of the tests in FILE,
335 traditionally `config.cache'. FILE defaults to `/dev/null' to
338 `--config-cache'
340 Alias for `--cache-file=config.cache'.
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