Lines Matching full:cache
21 #define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
104 #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
181 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
185 #define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */
186 #define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */
189 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
200 #define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */
201 #define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */
202 #define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */
203 #define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */
207 #define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */
208 #define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */
209 #define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */
210 #define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */
211 #define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */
248 #define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */
249 #define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */
251 #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
252 #define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */
253 #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
254 #define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
260 #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
261 #define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */
264 #define HID0_BTCD (1<<1) /* Branch target cache disable */
293 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
296 #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
298 #define SPRN_ICDBTRL 0x39e /* instruction cache debug tag register low */
299 #define SPRN_ICDBTRH 0x39f /* instruction cache debug tag register high */
302 #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
306 #define SPRN_INV0 0x370 /* Instruction Cache Normal Victim 0 */
307 #define SPRN_INV1 0x371 /* Instruction Cache Normal Victim 1 */
308 #define SPRN_INV2 0x372 /* Instruction Cache Normal Victim 2 */
309 #define SPRN_INV3 0x373 /* Instruction Cache Normal Victim 3 */
310 #define SPRN_ITV0 0x374 /* Instruction Cache Transient Victim 0 */
311 #define SPRN_ITV1 0x375 /* Instruction Cache Transient Victim 1 */
312 #define SPRN_ITV2 0x376 /* Instruction Cache Transient Victim 2 */
313 #define SPRN_ITV3 0x377 /* Instruction Cache Transient Victim 3 */
314 #define SPRN_IVLIM 0x399 /* Instruction Cache Victim Limit */
317 #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
474 #define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */
475 #define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */
476 #define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */
477 #define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
478 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
479 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
480 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
481 #define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
482 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
483 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
484 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
485 #define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */
486 #define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */
487 #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
488 #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
490 #define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */
491 #define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
492 #define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */
493 #define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */
495 #define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */
496 #define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
497 #define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */
498 #define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */
499 #define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */
537 #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
538 #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
539 #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */