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/nrf52832-nimble/rt-thread/components/net/uip/doc/html/
H A Dindex.hhc4 <param name="FrameName" value="right">
7 …itemap"><param name="Name" value="The uIP TCP/IP stack"><param name="Local" value="main.html"><par…
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10 …<OBJECT type="text/sitemap"><param name="Name" value="apps/dhcpc/dhcpc.c"><param name="ImageNumber…
11 …<OBJECT type="text/sitemap"><param name="Name" value="apps/dhcpc/dhcpc.h"><param name="ImageNumber…
12 …"><param name="Name" value="apps/hello-world/hello-world.c"><param name="Local" value="a00100.html…
13 …"><param name="Name" value="apps/hello-world/hello-world.h"><param name="Local" value="a00101.html…
14 …temap"><param name="Name" value="apps/resolv/resolv.c"><param name="Local" value="a00102.html"><pa…
15 …temap"><param name="Name" value="apps/resolv/resolv.h"><param name="Local" value="a00103.html"><pa…
16 …sitemap"><param name="Name" value="apps/smtp/smtp.c"><param name="Local" value="a00104.html"><para…
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H A Dindex.hhk4 <param name="FrameName" value="right">
7 …<LI><OBJECT type="text/sitemap"><param name="Local" value="a00151.html"><param name="Name" value="…
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/nrf52832-nimble/nordic/nrfx/mdk/
H A Dnrf51.svd86 <value>0</value>
123 <value>0</value>
128 <value>1</value>
136 <value>1</value>
156 <value>0</value>
161 <value>1</value>
169 <value>1</value>
189 <value>0</value>
194 <value>1</value>
206 <value>0</value>
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H A Dnrf52.svd170 <value>0</value>
175 <value>1</value>
218 <value>0x52832</value>
223 <value>0xFFFFFFFF</value>
245 <value>0x41414141</value>
250 <value>0x41414142</value>
255 <value>0x41414241</value>
260 <value>0x41414242</value>
265 <value>0x41414230</value>
270 <value>0x41414530</value>
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H A Dnrf52810.svd170 <value>0</value>
175 <value>1</value>
219 <value>0x52810</value>
224 <value>0xFFFFFFFF</value>
246 <value>0x41414141</value>
251 <value>0x41414130</value>
256 <value>0x41414241</value>
261 <value>0x41414242</value>
266 <value>0x41414230</value>
271 <value>0x41414341</value>
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H A Dnrf52840.svd170 <value>0</value>
175 <value>1</value>
219 <value>0x52840</value>
224 <value>0xFFFFFFFF</value>
246 <value>0x41414141</value>
251 <value>0x42414141</value>
256 <value>0x43414141</value>
261 <value>0x41414241</value>
266 <value>0x41414242</value>
271 <value>0x41414341</value>
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H A Dnrf9160.svd115 <value>0x9160</value>
137 <value>0x41414141</value>
142 <value>0x41414130</value>
164 <value>0x2000</value>
186 <value>0x100</value>
191 <value>0xFFFFFFFF</value>
213 <value>0x400</value>
265 <value>0x0000000</value>
270 <value>0xFFFFFFFF</value>
477 <value>0xFFFFFFFF</value>
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/nrf52832-nimble/nordic/nrfx/soc/
H A Dnrfx_atomic.h64 * @brief Function for storing a value to an atomic object and returning its previous value.
67 * @param[in] value Value to store.
69 * @return Previous value stored in the atomic object.
71 uint32_t nrfx_atomic_u32_fetch_store(nrfx_atomic_u32_t * p_data, uint32_t value);
74 * @brief Function for storing a value to an atomic object and returning its new value.
77 * @param[in] value Value to store.
79 * @return New value stored in the atomic object.
81 uint32_t nrfx_atomic_u32_store(nrfx_atomic_u32_t * p_data, uint32_t value);
85 * and returning its previous value.
88 * @param[in] value Value of the second operand in the OR operation.
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H A Dnrfx_atomic.c45 uint32_t nrfx_atomic_u32_fetch_store(nrfx_atomic_u32_t * p_data, uint32_t value) in nrfx_atomic_u32_fetch_store() argument
48 return __atomic_exchange_n(p_data, value, __ATOMIC_SEQ_CST); in nrfx_atomic_u32_fetch_store()
52 NRFX_ATOMIC_OP(mov, old_val, new_val, p_data, value); in nrfx_atomic_u32_fetch_store()
58 *p_data = value; in nrfx_atomic_u32_fetch_store()
64 uint32_t nrfx_atomic_u32_store(nrfx_atomic_u32_t * p_data, uint32_t value) in nrfx_atomic_u32_store() argument
67 __atomic_store_n(p_data, value, __ATOMIC_SEQ_CST); in nrfx_atomic_u32_store()
68 return value; in nrfx_atomic_u32_store()
72 NRFX_ATOMIC_OP(mov, old_val, new_val, p_data, value); in nrfx_atomic_u32_store()
77 *p_data = value; in nrfx_atomic_u32_store()
79 return value; in nrfx_atomic_u32_store()
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/nrf52832-nimble/packages/NimBLE-latest/nimble/host/
H A Dsyscfg.yml22 value: 1
28 value: 1
33 value: 0
39 value: 0
45 value: 1
50 value: 0
53 value: '"uart0"'
56 value: 1000000
60 This value should be a power of 2.
61 value: 64
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/nrf52832-nimble/packages/NimBLE-latest/nimble/host/mesh/
H A Dsyscfg.yml24 value: 1
30 value: 1
36 value: 0
42 value: 1
49 value: 1
54 using Node Identity. The given value is in seconds. The
56 be the appropriate value as well, so just leaving this as the
58 value: 60
64 value: 1
70 value: 1
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/nrf52832-nimble/rt-thread/components/CMSIS/Include/
H A Dcore_cmInstr.h113 This function reverses the byte order in integer value.
115 \param [in] value Value to reverse
116 \return Reversed value
125 \param [in] value Value to reverse
126 \return Reversed value
129 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) in __REV16() argument
136 /** \brief Reverse byte order in signed short value
138 This function reverses the byte order in a signed short value with sign extension to integer.
140 \param [in] value Value to reverse
141 \return Reversed value
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/nrf52832-nimble/nordic/cmsis/include/
H A Dcmsis_armcc.h55 \return Control Register value
66 \details Writes the given value to the Control Register.
67 \param [in] control Control Register value to set
79 \return IPSR Register value
91 \return APSR Register value
103 \return xPSR Register value
114 \details Returns the current value of the Process Stack Pointer (PSP).
115 \return PSP Register value
126 \details Assigns the given value to the Process Stack Pointer (PSP).
127 \param [in] topOfProcStack Process Stack Pointer value to set
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H A Dcmsis_armcc_V6.h70 \return Control Register value
85 \return non-secure Control Register value
99 \details Writes the given value to the Control Register.
100 \param [in] control Control Register value to set
111 \details Writes the given value to the non-secure Control Register when in secure state.
112 \param [in] control Control Register value to set
124 \return IPSR Register value
139 \return IPSR Register value
154 \return APSR Register value
169 \return APSR Register value
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/nrf52832-nimble/rt-thread/libcpu/c-sky/common/
H A Dcsi_instr.h113 \details Reverses the byte order in integer value.
114 \param [in] value Value to reverse
115 \return Reversed value
117 __ALWAYS_INLINE uint32_t __REV(uint32_t value) in __REV() argument
119 return __builtin_bswap32(value); in __REV()
126 \param [in] value Value to reverse
127 \return Reversed value
129 __ALWAYS_INLINE uint32_t __REV16(uint32_t value) in __REV16() argument
133 __ASM volatile("revh %0, %1" : __CSI_GCC_OUT_REG(result) : __CSI_GCC_USE_REG(value)); in __REV16()
135 result = ((value & 0xFF000000) >> 8) | ((value & 0x00FF0000) << 8) | in __REV16()
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/nrf52832-nimble/rt-thread/libcpu/arm/arm926/
H A Dmmu.c17 register rt_uint32_t value; in mmu_setttbase() local
21 * in that case access controlled by permission value in mmu_setttbase()
24 value = 0; in mmu_setttbase()
25 __asm volatile{ mcr p15, 0, value, c8, c7, 0 } in mmu_setttbase()
26 value = 0x55555555; in mmu_setttbase()
27 __asm volatile { mcr p15, 0, value, c3, c0, 0 } in mmu_setttbase()
38 register rt_uint32_t value; in mmu_enable() local
42 mrc p15, 0, value, c1, c0, 0 in mmu_enable()
43 orr value, value, #0x01 in mmu_enable()
44 mcr p15, 0, value, c1, c0, 0 in mmu_enable()
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/nrf52832-nimble/packages/NimBLE-latest/nimble/controller/
H A Dsyscfg.yml24 value: 1
29 value: 1
34 value: 1
39 value: 0
44 value: 0
49 # NOTE: 'the' master sca is an enumerated value based on the sca. Rather
50 # than have a piece of code calculate this value, the developer must set
51 # this value based on the value of the SCA using the following table:
70 value: '60' # in ppm
73 description: 'Enumerated value based on our sca'
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/nrf52832-nimble/rt-thread/components/drivers/sensors/
H A Dmpu6050_sensor.cpp65 int MPU6050::read_reg(rt_uint8_t reg, rt_uint8_t *value) in read_reg() argument
76 msgs[1].buf = (rt_uint8_t *)value; in read_reg()
85 int MPU6050::read_buffer(rt_uint8_t reg, rt_uint8_t* value, rt_size_t size) in read_buffer() argument
96 msgs[1].buf = (rt_uint8_t *)value; in read_buffer()
105 int MPU6050::write_reg(rt_uint8_t reg, rt_uint8_t value) in write_reg() argument
116 msgs[1].buf = (rt_uint8_t *)&value; in write_reg()
131 rt_uint8_t value[6] = {0}; in MPU6050_Accelerometer() local
157 read_buffer(MPU6050_ACCEL_XOUT_H, value, 6); in MPU6050_Accelerometer()
159 x += (((rt_int16_t)value[0] << 8) | value[1]); in MPU6050_Accelerometer()
160 y += (((rt_int16_t)value[2] << 8) | value[3]); in MPU6050_Accelerometer()
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H A Dbmi055_sensor.cpp63 int BMI055::read_reg(rt_uint8_t reg, rt_uint8_t *value) in read_reg() argument
74 msgs[1].buf = (rt_uint8_t *)value; in read_reg()
83 int BMI055::read_buffer(rt_uint8_t reg, rt_uint8_t* value, rt_size_t size) in read_buffer() argument
94 msgs[1].buf = (rt_uint8_t *)value; in read_buffer()
103 int BMI055::write_reg(rt_uint8_t reg, rt_uint8_t value) in write_reg() argument
114 msgs[1].buf = (rt_uint8_t *)&value; in write_reg()
129 rt_uint8_t value[6] = {0}; in BMI055_Accelerometer() local
152 read_buffer(BMI055_ACCD_X_LSB, value, 6); /*ACCD_X_LSB P47 */ in BMI055_Accelerometer()
154 x += (((rt_int16_t)value[1] << 8) | value[0]); in BMI055_Accelerometer()
155 y += (((rt_int16_t)value[3] << 8) | value[2]); in BMI055_Accelerometer()
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/nrf52832-nimble/packages/NimBLE-latest/nimble/host/mesh/src/
H A Datomic.h30 * value of @a target equals @a old_value, @a target is set to @a new_value.
31 * If the current value of @a target does not equal @a old_value, @a target
35 * @param old_value Original value to compare against.
36 * @param new_value New value to store.
54 * @param value Value to add.
56 * @return Previous value of @a target.
58 static inline atomic_val_t atomic_add(atomic_t *target, atomic_val_t value) in atomic_add() argument
60 return __atomic_fetch_add(target, value, __ATOMIC_SEQ_CST); in atomic_add()
70 * @param value Value to subtract.
72 * @return Previous value of @a target.
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/nrf52832-nimble/rt-thread/libcpu/mips/xburst/
H A Dmipscfg.c82 static void CP0_status_analyze(unsigned long value) in CP0_status_analyze() argument
84 if(value & (1<<26)) in CP0_status_analyze()
86 if(value & (1<<23)) in CP0_status_analyze()
88 if(value & (1<<22)) in CP0_status_analyze()
90 if(value & (1<<20)) in CP0_status_analyze()
92 if(value & (1<<19)) in CP0_status_analyze()
94 if(value & (1<<20)) in CP0_status_analyze()
96 if(value & (0xFF<<8)) in CP0_status_analyze()
97 rt_kprintf(" IM:0x%02X", (value >> 8) & 0xFF); in CP0_status_analyze()
98 if(value & (1<<7)) in CP0_status_analyze()
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/nrf52832-nimble/rt-thread/libcpu/arm/armv6/
H A Dmmu.c15 register rt_uint32_t value; in mmu_setttbase() local
19 * in that case access controlled by permission value in mmu_setttbase()
22 value = 0; in mmu_setttbase()
25 mcr p15, 0, value, c8, c7, 0 in mmu_setttbase()
28 value = 0x55555555; in mmu_setttbase()
31 mcr p15, 0, value, c3, c0, 0 in mmu_setttbase()
46 register rt_uint32_t value; in mmu_enable() local
50 mrc p15, 0, value, c1, c0, 0 in mmu_enable()
51 orr value, value, #0x01 in mmu_enable()
52 mcr p15, 0, value, c1, c0, 0 in mmu_enable()
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H A Dcpuport.c69 rt_uint32_t value; in cache_enable() local
73 mrc p15, 0, value, c1, c0, 0 in cache_enable()
74 orr value, value, bit in cache_enable()
75 mcr p15, 0, value, c1, c0, 0 in cache_enable()
81 rt_uint32_t value; in cache_disable() local
85 mrc p15, 0, value, c1, c0, 0 in cache_disable()
86 bic value, value, bit in cache_disable()
87 mcr p15, 0, value, c1, c0, 0 in cache_disable()
181 * in value and return the index of that bit.
183 * Bits are numbered starting at 1 (the least significant bit). A return value of
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/nrf52832-nimble/rt-thread/libcpu/arm/dm36x/
H A Dmmu.c15 register rt_uint32_t value; in mmu_setttbase() local
19 * in that case access controlled by permission value in mmu_setttbase()
22 value = 0; in mmu_setttbase()
25 mcr p15, 0, value, c8, c7, 0 in mmu_setttbase()
28 value = 0x55555555; in mmu_setttbase()
31 mcr p15, 0, value, c3, c0, 0 in mmu_setttbase()
46 register rt_uint32_t value; in mmu_enable() local
50 mrc p15, 0, value, c1, c0, 0 in mmu_enable()
51 orr value, value, #0x01 in mmu_enable()
52 mcr p15, 0, value, c1, c0, 0 in mmu_enable()
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H A Dcpuport.c67 rt_uint32_t value; in cache_enable() local
71 mrc p15, 0, value, c1, c0, 0 in cache_enable()
72 orr value, value, bit in cache_enable()
73 mcr p15, 0, value, c1, c0, 0 in cache_enable()
79 rt_uint32_t value; in cache_disable() local
83 mrc p15, 0, value, c1, c0, 0 in cache_disable()
84 bic value, value, bit in cache_disable()
85 mcr p15, 0, value, c1, c0, 0 in cache_disable()
179 * in value and return the index of that bit.
181 * Bits are numbered starting at 1 (the least significant bit). A return value of
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