Lines Matching full:value
17 register rt_uint32_t value; in mmu_setttbase() local
21 * in that case access controlled by permission value in mmu_setttbase()
24 value = 0; in mmu_setttbase()
25 __asm volatile{ mcr p15, 0, value, c8, c7, 0 } in mmu_setttbase()
26 value = 0x55555555; in mmu_setttbase()
27 __asm volatile { mcr p15, 0, value, c3, c0, 0 } in mmu_setttbase()
38 register rt_uint32_t value; in mmu_enable() local
42 mrc p15, 0, value, c1, c0, 0 in mmu_enable()
43 orr value, value, #0x01 in mmu_enable()
44 mcr p15, 0, value, c1, c0, 0 in mmu_enable()
50 register rt_uint32_t value; in mmu_disable() local
54 mrc p15, 0, value, c1, c0, 0 in mmu_disable()
55 bic value, value, #0x01 in mmu_disable()
56 mcr p15, 0, value, c1, c0, 0 in mmu_disable()
62 register rt_uint32_t value; in mmu_enable_icache() local
66 mrc p15, 0, value, c1, c0, 0 in mmu_enable_icache()
67 orr value, value, #0x1000 in mmu_enable_icache()
68 mcr p15, 0, value, c1, c0, 0 in mmu_enable_icache()
74 register rt_uint32_t value; in mmu_enable_dcache() local
78 mrc p15, 0, value, c1, c0, 0 in mmu_enable_dcache()
79 orr value, value, #0x04 in mmu_enable_dcache()
80 mcr p15, 0, value, c1, c0, 0 in mmu_enable_dcache()
86 register rt_uint32_t value; in mmu_disable_icache() local
90 mrc p15, 0, value, c1, c0, 0 in mmu_disable_icache()
91 bic value, value, #0x1000 in mmu_disable_icache()
92 mcr p15, 0, value, c1, c0, 0 in mmu_disable_icache()
98 register rt_uint32_t value; in mmu_disable_dcache() local
102 mrc p15, 0, value, c1, c0, 0 in mmu_disable_dcache()
103 bic value, value, #0x04 in mmu_disable_dcache()
104 mcr p15, 0, value, c1, c0, 0 in mmu_disable_dcache()
110 register rt_uint32_t value; in mmu_enable_alignfault() local
114 mrc p15, 0, value, c1, c0, 0 in mmu_enable_alignfault()
115 orr value, value, #0x02 in mmu_enable_alignfault()
116 mcr p15, 0, value, c1, c0, 0 in mmu_enable_alignfault()
122 register rt_uint32_t value; in mmu_disable_alignfault() local
126 mrc p15, 0, value, c1, c0, 0 in mmu_disable_alignfault()
127 bic value, value, #0x02 in mmu_disable_alignfault()
128 mcr p15, 0, value, c1, c0, 0 in mmu_disable_alignfault()
178 register rt_uint32_t value; in mmu_invalidate_tlb() local
180 value = 0; in mmu_invalidate_tlb()
181 __asm volatile { mcr p15, 0, value, c8, c7, 0 } in mmu_invalidate_tlb()
186 register rt_uint32_t value; in mmu_invalidate_icache() local
188 value = 0; in mmu_invalidate_icache()
190 __asm volatile { mcr p15, 0, value, c7, c5, 0 } in mmu_invalidate_icache()
196 register rt_uint32_t value; in mmu_invalidate_dcache_all() local
198 value = 0; in mmu_invalidate_dcache_all()
200 __asm volatile { mcr p15, 0, value, c7, c6, 0 } in mmu_invalidate_dcache_all()
206 register rt_uint32_t value; in mmu_setttbase() local
210 * in that case access controlled by permission value in mmu_setttbase()
213 value = 0; in mmu_setttbase()
214 asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); in mmu_setttbase()
216 value = 0x55555555; in mmu_setttbase()
217 asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); in mmu_setttbase()