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/nrf52832-nimble/nordic/nrfx/hal/
H A Dnrf_ppi.h57 NRF_PPI_CHANNEL0 = PPI_CHEN_CH0_Pos, /**< Channel 0. */
58 NRF_PPI_CHANNEL1 = PPI_CHEN_CH1_Pos, /**< Channel 1. */
59 NRF_PPI_CHANNEL2 = PPI_CHEN_CH2_Pos, /**< Channel 2. */
60 NRF_PPI_CHANNEL3 = PPI_CHEN_CH3_Pos, /**< Channel 3. */
61 NRF_PPI_CHANNEL4 = PPI_CHEN_CH4_Pos, /**< Channel 4. */
62 NRF_PPI_CHANNEL5 = PPI_CHEN_CH5_Pos, /**< Channel 5. */
63 NRF_PPI_CHANNEL6 = PPI_CHEN_CH6_Pos, /**< Channel 6. */
64 NRF_PPI_CHANNEL7 = PPI_CHEN_CH7_Pos, /**< Channel 7. */
65 NRF_PPI_CHANNEL8 = PPI_CHEN_CH8_Pos, /**< Channel 8. */
66 NRF_PPI_CHANNEL9 = PPI_CHEN_CH9_Pos, /**< Channel 9. */
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H A Dnrf_dppi.h49 /** @brief DPPI channel groups. */
52 NRF_DPPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */
53 NRF_DPPI_CHANNEL_GROUP1 = 1, /**< Channel group 1. */
54 NRF_DPPI_CHANNEL_GROUP2 = 2, /**< Channel group 2. */
55 NRF_DPPI_CHANNEL_GROUP3 = 3, /**< Channel group 3. */
56 NRF_DPPI_CHANNEL_GROUP4 = 4, /**< Channel group 4. */
57 NRF_DPPI_CHANNEL_GROUP5 = 5 /**< Channel group 5. */
63 …NRF_DPPI_TASK_CHG0_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[0].EN), /**< Enable channel group 0. …
64 …NRF_DPPI_TASK_CHG0_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[0].DIS), /**< Disable channel group 0.…
65 …NRF_DPPI_TASK_CHG1_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[1].EN), /**< Enable channel group 1. …
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H A Dnrf_saadc.h98 * @brief Analog-to-digital converter channel resistor control.
150 * @brief Analog-to-digital converter channel mode.
160 * @brief Analog-to-digital converter channel burst mode.
268 * @brief Analog-to-digital converter channel configuration structure.
330 * @param[in] channel Channel through which to subscribe events.
333 uint8_t channel);
348 * @param[in] channel Channel through which to publish the event.
351 uint8_t channel);
365 * @param[in] channel Channel number.
370 __STATIC_INLINE volatile uint32_t * nrf_saadc_event_limit_address_get(uint8_t channel, nrf_saadc_li…
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H A Dnrf_timer.h100 …= offsetof(NRF_TIMER_Type, TASKS_CAPTURE[0]), ///< Task for capturing the timer value on channel 0.
101 …= offsetof(NRF_TIMER_Type, TASKS_CAPTURE[1]), ///< Task for capturing the timer value on channel 1.
102 …= offsetof(NRF_TIMER_Type, TASKS_CAPTURE[2]), ///< Task for capturing the timer value on channel 2.
103 …= offsetof(NRF_TIMER_Type, TASKS_CAPTURE[3]), ///< Task for capturing the timer value on channel 3.
105 …= offsetof(NRF_TIMER_Type, TASKS_CAPTURE[4]), ///< Task for capturing the timer value on channel 4.
108 …= offsetof(NRF_TIMER_Type, TASKS_CAPTURE[5]), ///< Task for capturing the timer value on channel 5.
119 …ER_EVENT_COMPARE0 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[0]), ///< Event from compare channel 0.
120 …ER_EVENT_COMPARE1 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[1]), ///< Event from compare channel 1.
121 …ER_EVENT_COMPARE2 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[2]), ///< Event from compare channel 2.
122 …ER_EVENT_COMPARE3 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[3]), ///< Event from compare channel 3.
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H A Dnrf_egu.h125 /**@brief Function for getting max channel number of given EGU.
154 * @param channel Channel number.
157 uint8_t channel);
163 * @param channel Channel number.
165 __STATIC_INLINE nrf_egu_task_t nrf_egu_task_trigger_get(NRF_EGU_Type * NRF_EGUx, uint8_t channel);
198 * @param channel Channel number.
201 uint8_t channel);
207 * @param channel Channel number.
210 uint8_t channel);
243 * @param channel Channel number.
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H A Dnrf_rtc.h94 …T_COMPARE0_MASK = RTC_INTENSET_COMPARE0_Msk, /**< RTC interrupt from compare event on channel 0. */
95 …T_COMPARE1_MASK = RTC_INTENSET_COMPARE1_Msk, /**< RTC interrupt from compare event on channel 1. */
96 …T_COMPARE2_MASK = RTC_INTENSET_COMPARE2_Msk, /**< RTC interrupt from compare event on channel 2. */
97 …T_COMPARE3_MASK = RTC_INTENSET_COMPARE3_Msk /**< RTC interrupt from compare event on channel 3. */
101 * @brief Function for setting a compare value for a channel.
104 * @param[in] ch Channel.
110 * @brief Function for returning the compare value for a channel.
113 * @param[in] ch Channel.
161 * @param[in] channel Channel through which to subscribe events.
165 uint8_t channel);
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H A Dnrf_pwm.h50 * function call to specify that a given output channel shall not be
150 …dividual, ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; 3rd in channel 2; 4th i…
151 …WM_DECODER_LOAD_WaveForm ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; ... ;…
188 uint16_t channel_0; ///< Duty cycle value for channel 0.
189 uint16_t channel_1; ///< Duty cycle value for channel 1.
190 uint16_t channel_2; ///< Duty cycle value for channel 2.
191 uint16_t channel_3; ///< Duty cycle value for channel 3.
199 uint16_t channel_0; ///< Duty cycle value for channel 0.
200 uint16_t channel_1; ///< Duty cycle value for channel 1.
201 uint16_t channel_2; ///< Duty cycle value for channel 2.
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H A Dnrf_pdm.h187 * @param[in] channel Channel through which to subscribe events.
190 uint8_t channel);
205 * @param[in] channel Channel through which to publish the event.
208 uint8_t channel);
283 * @param[in] gain_l Left channel gain.
284 * @param[in] gain_r Right channel gain.
291 * @param[out] p_gain_l Left channel gain.
292 * @param[out] p_gain_r Right channel gain.
362 uint8_t channel) in nrf_pdm_subscribe_set() argument
365 ((uint32_t)channel | PDM_SUBSCRIBE_START_EN_Msk); in nrf_pdm_subscribe_set()
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/nrf52832-nimble/nordic/nrfx/drivers/include/
H A Dnrfx_ppi.h70 * This function disables all channels and clears the channel groups.
75 * @brief Function for allocating a PPI channel.
76 * @details This function allocates the first unused PPI channel.
78 * @param[out] p_channel Pointer to the PPI channel that has been allocated.
80 * @retval NRFX_SUCCESS If the channel was successfully allocated.
81 * @retval NRFX_ERROR_NO_MEM If there is no available channel to be used.
86 * @brief Function for freeing a PPI channel.
87 * @details This function also disables the chosen channel.
89 * @param[in] channel PPI channel to be freed.
91 * @retval NRFX_SUCCESS If the channel was successfully freed.
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H A Dnrfx_dppi.h53 * @brief Function for allocating a DPPI channel.
54 * @details This function allocates the first unused DPPI channel.
56 * @param[out] p_channel Pointer to the DPPI channel number that has been allocated.
58 * @retval NRFX_SUCCESS If the channel was successfully allocated.
59 * @retval NRFX_ERROR_NO_MEM If there is no available channel to be used.
64 * @brief Function for freeing a DPPI channel.
65 * @details This function also disables the chosen channel.
67 * @param[in] channel DPPI channel to be freed.
69 * @retval NRFX_SUCCESS If the channel was successfully freed.
70 * @retval NRFX_ERROR_INVALID_PARAM If the specified channel is not allocated.
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H A Dnrfx_timer.h215 * @param[in] channel Capture channel number.
220 uint32_t channel);
237 * @param[in] channel Compare channel number.
242 uint32_t channel);
248 * @param[in] cc_channel Capture channel number.
256 * @brief Function for returning the capture value from a specific channel.
258 * Use this function to read channel values when PPI is used for capturing.
261 * @param[in] cc_channel Capture channel number.
269 * @brief Function for setting the timer channel in compare mode.
272 * @param[in] cc_channel Compare channel number.
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H A Dnrfx_saadc.h142 uint8_t channel; ///< Channel on which the limit was detected. member
197 * @brief Function for initializing an SAADC channel.
199 * This function configures and enables the channel.
203 * @retval NRFX_ERROR_NO_MEM If the specified channel was already allocated.
205 nrfx_err_t nrfx_saadc_channel_init(uint8_t channel,
210 * @brief Function for uninitializing an SAADC channel.
215 nrfx_err_t nrfx_saadc_channel_uninit(uint8_t channel);
233 * @param[in] channel Channel.
239 nrfx_err_t nrfx_saadc_sample_convert(uint8_t channel, nrf_saadc_value_t * p_value);
290 * @brief Function for setting the SAADC channel limits.
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H A Dnrfx_adc.h55 NRFX_ADC_EVT_SAMPLE, ///< Event generated when the requested channel is sampled.
88 /**@brief Macro for initializing the ADC channel with the default configuration. */
105 * @brief ADC channel.
112 nrfx_adc_channel_t * p_next; ///< Pointer to the next enabled channel (for internal use).
113 nrf_adc_config_t config; ///< ADC configuration for the current channel.
162 * @brief Function for enabling an ADC channel.
164 * This function configures and enables the channel. When @ref nrfx_adc_buffer_convert is
170 * @note The channel instance variable @p p_channel is used by the driver as an item
176 * @brief Function for disabling an ADC channel.
194 * This function triggers single ADC sampling. If more than one channel is enabled, the driver
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/nrf52832-nimble/nordic/nrfx/drivers/src/
H A Dnrfx_ppi.c42 …nels_allocated; /**< Bitmap representing channels availability. 1 when a channel is allocated, 0 o…
60 * @brief Check whether a channel is a programmable channel and can be used by an application.
62 * @param[in] channel Channel to check.
64 * @retval true The channel is a programmable application channel.
65 * @retval false The channel is used by a stack (for example SoftDevice) or is preprogrammed.
67 __STATIC_INLINE bool is_programmable_app_channel(nrf_ppi_channel_t channel) in is_programmable_app_channel() argument
69 return ((NRFX_PPI_PROG_APP_CHANNELS_MASK & nrfx_ppi_channel_to_mask(channel)) != 0); in is_programmable_app_channel()
76 * @param[in] channel_mask Channel mask to check.
79 * @retval false At least one specified channel is used by a stack (for example SoftDevice).
89 * @brief Check whether a channel can be used by an application.
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H A Dnrfx_dppi.c64 __STATIC_INLINE bool channel_is_allocated(uint8_t channel) in channel_is_allocated() argument
66 return ((m_allocated_channels & DPPI_BIT_SET(channel)) != 0); in channel_is_allocated()
106 uint8_t channel = 0; in nrfx_dppi_channel_alloc() local
115 // Find first free channel in nrfx_dppi_channel_alloc()
116 while (!(remaining_channels & DPPI_BIT_SET(channel))) in nrfx_dppi_channel_alloc()
118 channel++; in nrfx_dppi_channel_alloc()
121 m_allocated_channels |= DPPI_BIT_SET(channel); in nrfx_dppi_channel_alloc()
122 *p_channel = channel; in nrfx_dppi_channel_alloc()
125 NRFX_LOG_INFO("Allocated channel: %d.", channel); in nrfx_dppi_channel_alloc()
129 nrfx_err_t nrfx_dppi_channel_free(uint8_t channel) in nrfx_dppi_channel_free() argument
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H A Dnrfx_saadc.c83 #define LOW_LIMIT_TO_FLAG(channel) ((2 * channel + 1)) argument
84 #define HIGH_LIMIT_TO_FLAG(channel) ((2 * channel)) argument
190 evt.data.limit.channel = LIMIT_EVENT_TO_CHANNEL(event); in nrfx_saadc_irq_handler()
192 NRFX_LOG_DEBUG("Event limit, channel: %d, limit type: %d.", in nrfx_saadc_irq_handler()
193 evt.data.limit.channel, in nrfx_saadc_irq_handler()
265 for (uint32_t channel = 0; channel < NRF_SAADC_CHANNEL_COUNT; ++channel) in nrfx_saadc_uninit() local
267 if (m_cb.psel[channel].pselp != NRF_SAADC_INPUT_DISABLED) in nrfx_saadc_uninit()
269 nrfx_err_t err_code = nrfx_saadc_channel_uninit(channel); in nrfx_saadc_uninit()
278 nrfx_err_t nrfx_saadc_channel_init(uint8_t channel, in nrfx_saadc_channel_init() argument
282 NRFX_ASSERT(channel < NRF_SAADC_CHANNEL_COUNT); in nrfx_saadc_channel_init()
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H A Dnrfx_rtc.c137 nrfx_err_t nrfx_rtc_cc_disable(nrfx_rtc_t const * const p_instance, uint32_t channel) in nrfx_rtc_cc_disable() argument
140 NRFX_ASSERT(channel<p_instance->cc_channel_count); in nrfx_rtc_cc_disable()
143 uint32_t int_mask = RTC_CHANNEL_INT_MASK(channel); in nrfx_rtc_cc_disable()
144 nrf_rtc_event_t event = RTC_CHANNEL_EVENT_ADDR(channel); in nrfx_rtc_cc_disable()
160 NRFX_LOG_INFO("RTC id: %d, channel disabled: %lu.", p_instance->instance_id, channel); in nrfx_rtc_cc_disable()
167 uint32_t channel, in nrfx_rtc_cc_set() argument
172 NRFX_ASSERT(channel<p_instance->cc_channel_count); in nrfx_rtc_cc_set()
175 uint32_t int_mask = RTC_CHANNEL_INT_MASK(channel); in nrfx_rtc_cc_set()
176 nrf_rtc_event_t event = RTC_CHANNEL_EVENT_ADDR(channel); in nrfx_rtc_cc_set()
184 nrf_rtc_cc_set(p_instance->p_reg,channel,val); in nrfx_rtc_cc_set()
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H A Dnrfx_gpiote.c181 __STATIC_INLINE nrfx_gpiote_evt_handler_t channel_handler_get(uint32_t channel) in channel_handler_get() argument
183 return m_cb.handlers[channel]; in channel_handler_get()
187 static int8_t channel_port_alloc(uint32_t pin, nrfx_gpiote_evt_handler_t handler, bool channel) in channel_port_alloc() argument
192 uint32_t start_idx = channel ? 0 : GPIOTE_CH_NUM; in channel_port_alloc()
194 channel ? GPIOTE_CH_NUM : (GPIOTE_CH_NUM + NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS); in channel_port_alloc()
202 pin_in_use_by_te_set(pin, i, handler, channel); in channel_port_alloc()
309 int8_t channel = channel_port_alloc(pin, NULL, true); in nrfx_gpiote_out_init() local
311 if (channel != NO_CHANNELS) in nrfx_gpiote_out_init()
313 nrf_gpiote_task_configure((uint32_t)channel, in nrfx_gpiote_out_init()
513 /* Only one GPIOTE channel can be assigned to one physical pin. */ in nrfx_gpiote_in_init()
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/nrf52832-nimble/packages/NimBLE-latest/nimble/host/include/host/
H A Dble_hs_hci.h37 * Queries the controller for the channel map used with the specified
38 * connection. The channel map is represented as an array of five bytes, with
39 * each bit corresponding to an individual channel. The array is interpreted
41 * map[0] & 0x01 --> Channel 0.
42 * map[0] & 0x02 --> Channel 1.
44 * map[1] & 0x01 --> Channel 8.
48 * If a bit is 1, the corresponding channel is used. Otherwise, the channel is
51 * @param conn_handle The handle of the connection whose channel map
53 * @param out_chan_map On success, the retrieved channel map gets
66 * Instructs the controller to use the specified channel map. The channel map
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/nrf52832-nimble/rt-thread/libcpu/ppc/ppc405/include/asm/
H A Dppc405.h37 #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
42 #define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
47 #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
52 #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */
556 #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/
557 #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
561 #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/
562 #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
566 #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */
567 #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */
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/nrf52832-nimble/rt-thread/components/drivers/misc/
H A Dadc.c86 rt_uint32_t rt_adc_read(rt_adc_device_t dev, rt_uint32_t channel) in rt_adc_read() argument
92 dev->ops->convert(dev, channel, &value); in rt_adc_read()
97 rt_err_t rt_adc_enable(rt_adc_device_t dev, rt_uint32_t channel) in rt_adc_enable() argument
104 result = dev->ops->enabled(dev, channel, RT_TRUE); in rt_adc_enable()
114 rt_err_t rt_adc_disable(rt_adc_device_t dev, rt_uint32_t channel) in rt_adc_disable() argument
121 result = dev->ops->enabled(dev, channel, RT_FALSE); in rt_adc_disable()
168 …rt_kprintf("%s channel %d enables %s \n", adc_device->parent.parent.name, atoi(argv[2]), result_st… in adc()
172 rt_kprintf("adc enable <channel> - enable adc channel\n"); in adc()
180 …rt_kprintf("%s channel %d read value is 0x%08X \n", adc_device->parent.parent.name, atoi(argv[2])… in adc()
184 rt_kprintf("adc read <channel> - read adc value on the channel\n"); in adc()
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H A Drt_drv_pwm.c30 pos: channel
41 configuration.channel = pos; in _pwm_read()
58 pos: channel
69 configuration.channel = pos; in _pwm_write()
129 rt_err_t rt_pwm_enable(struct rt_device_pwm *device, int channel) in rt_pwm_enable() argument
139 configuration.channel = channel; in rt_pwm_enable()
145 rt_err_t rt_pwm_disable(struct rt_device_pwm *device, int channel) in rt_pwm_disable() argument
155 configuration.channel = channel; in rt_pwm_disable()
161 rt_err_t rt_pwm_set(struct rt_device_pwm *device, int channel, rt_uint32_t period, rt_uint32_t puls… in rt_pwm_set() argument
171 configuration.channel = channel; in rt_pwm_set()
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/nrf52832-nimble/rt-thread/components/vbus/
H A Dvbus.h20 /** Post data on channel.
22 * @param chnr the channel number
64 /** Request a channel.
66 * @return channel number. Negative if error happened.
70 /** Close channel @chnr */
73 /** Set the water mark level for posting into the channel @chnr. */
75 /** Set the water mark level for receiving from the channel @chnr. */
81 /* On a packet received in channel. */
85 /* On the channel has been closed. */
106 /** Push a data package into the receive queue of the channel @chnr. */
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/nrf52832-nimble/nordic/nrfx/mdk/
H A Dnrf51_bitfields.h2188 /* Description: Channel configuration registers. */
2190 /* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
2212 #define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */
2213 #define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */
3264 /* Description: Channel enable. */
3266 /* Bit 31 : Enable PPI channel 31. */
3269 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */
3270 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */
3272 /* Bit 30 : Enable PPI channel 30. */
3275 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */
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/nrf52832-nimble/rt-thread/components/drivers/include/drivers/
H A Dadc.h19 rt_err_t (*enabled)(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled);
20 rt_err_t (*convert)(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value);
38 rt_uint32_t rt_adc_read(rt_adc_device_t dev, rt_uint32_t channel);
39 rt_err_t rt_adc_enable(rt_adc_device_t dev, rt_uint32_t channel);
40 rt_err_t rt_adc_disable(rt_adc_device_t dev, rt_uint32_t channel);

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