Lines Matching full:channel

2188 /* Description: Channel configuration registers. */
2190 /* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
2212 #define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */
2213 #define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */
3264 /* Description: Channel enable. */
3266 /* Bit 31 : Enable PPI channel 31. */
3269 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */
3270 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */
3272 /* Bit 30 : Enable PPI channel 30. */
3275 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */
3276 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */
3278 /* Bit 29 : Enable PPI channel 29. */
3281 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */
3282 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */
3284 /* Bit 28 : Enable PPI channel 28. */
3287 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */
3288 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */
3290 /* Bit 27 : Enable PPI channel 27. */
3293 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */
3294 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */
3296 /* Bit 26 : Enable PPI channel 26. */
3299 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */
3300 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */
3302 /* Bit 25 : Enable PPI channel 25. */
3305 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */
3306 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */
3308 /* Bit 24 : Enable PPI channel 24. */
3311 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */
3312 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */
3314 /* Bit 23 : Enable PPI channel 23. */
3317 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */
3318 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */
3320 /* Bit 22 : Enable PPI channel 22. */
3323 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */
3324 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */
3326 /* Bit 21 : Enable PPI channel 21. */
3329 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */
3330 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */
3332 /* Bit 20 : Enable PPI channel 20. */
3335 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */
3336 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */
3338 /* Bit 15 : Enable PPI channel 15. */
3341 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */
3342 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */
3344 /* Bit 14 : Enable PPI channel 14. */
3347 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */
3348 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */
3350 /* Bit 13 : Enable PPI channel 13. */
3353 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */
3354 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */
3356 /* Bit 12 : Enable PPI channel 12. */
3359 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */
3360 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */
3362 /* Bit 11 : Enable PPI channel 11. */
3365 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */
3366 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */
3368 /* Bit 10 : Enable PPI channel 10. */
3371 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */
3372 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */
3374 /* Bit 9 : Enable PPI channel 9. */
3377 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */
3378 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */
3380 /* Bit 8 : Enable PPI channel 8. */
3383 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */
3384 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */
3386 /* Bit 7 : Enable PPI channel 7. */
3389 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */
3390 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */
3392 /* Bit 6 : Enable PPI channel 6. */
3395 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */
3396 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */
3398 /* Bit 5 : Enable PPI channel 5. */
3401 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */
3402 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */
3404 /* Bit 4 : Enable PPI channel 4. */
3407 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */
3408 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */
3410 /* Bit 3 : Enable PPI channel 3. */
3413 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */
3414 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */
3416 /* Bit 2 : Enable PPI channel 2. */
3419 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */
3420 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */
3422 /* Bit 1 : Enable PPI channel 1. */
3425 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */
3426 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */
3428 /* Bit 0 : Enable PPI channel 0. */
3431 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */
3432 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */
3435 /* Description: Channel enable set. */
3437 /* Bit 31 : Enable PPI channel 31. */
3440 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */
3441 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */
3442 #define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */
3444 /* Bit 30 : Enable PPI channel 30. */
3447 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */
3448 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */
3449 #define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */
3451 /* Bit 29 : Enable PPI channel 29. */
3454 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */
3455 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */
3456 #define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */
3458 /* Bit 28 : Enable PPI channel 28. */
3461 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */
3462 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */
3463 #define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */
3465 /* Bit 27 : Enable PPI channel 27. */
3468 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */
3469 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */
3470 #define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */
3472 /* Bit 26 : Enable PPI channel 26. */
3475 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */
3476 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */
3477 #define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */
3479 /* Bit 25 : Enable PPI channel 25. */
3482 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */
3483 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */
3484 #define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */
3486 /* Bit 24 : Enable PPI channel 24. */
3489 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */
3490 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */
3491 #define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */
3493 /* Bit 23 : Enable PPI channel 23. */
3496 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */
3497 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */
3498 #define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */
3500 /* Bit 22 : Enable PPI channel 22. */
3503 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */
3504 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */
3505 #define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */
3507 /* Bit 21 : Enable PPI channel 21. */
3510 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */
3511 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */
3512 #define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */
3514 /* Bit 20 : Enable PPI channel 20. */
3517 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */
3518 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */
3519 #define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */
3521 /* Bit 15 : Enable PPI channel 15. */
3524 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */
3525 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */
3526 #define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */
3528 /* Bit 14 : Enable PPI channel 14. */
3531 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */
3532 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */
3533 #define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */
3535 /* Bit 13 : Enable PPI channel 13. */
3538 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */
3539 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */
3540 #define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */
3542 /* Bit 12 : Enable PPI channel 12. */
3545 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */
3546 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */
3547 #define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */
3549 /* Bit 11 : Enable PPI channel 11. */
3552 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */
3553 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */
3554 #define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */
3556 /* Bit 10 : Enable PPI channel 10. */
3559 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */
3560 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */
3561 #define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */
3563 /* Bit 9 : Enable PPI channel 9. */
3566 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */
3567 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */
3568 #define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */
3570 /* Bit 8 : Enable PPI channel 8. */
3573 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */
3574 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */
3575 #define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */
3577 /* Bit 7 : Enable PPI channel 7. */
3580 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */
3581 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */
3582 #define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */
3584 /* Bit 6 : Enable PPI channel 6. */
3587 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */
3588 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */
3589 #define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */
3591 /* Bit 5 : Enable PPI channel 5. */
3594 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */
3595 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */
3596 #define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */
3598 /* Bit 4 : Enable PPI channel 4. */
3601 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */
3602 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */
3603 #define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */
3605 /* Bit 3 : Enable PPI channel 3. */
3608 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */
3609 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */
3610 #define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */
3612 /* Bit 2 : Enable PPI channel 2. */
3615 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */
3616 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */
3617 #define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */
3619 /* Bit 1 : Enable PPI channel 1. */
3622 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */
3623 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */
3624 #define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */
3626 /* Bit 0 : Enable PPI channel 0. */
3629 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */
3630 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */
3631 #define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */
3634 /* Description: Channel enable clear. */
3636 /* Bit 31 : Disable PPI channel 31. */
3639 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */
3640 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */
3641 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */
3643 /* Bit 30 : Disable PPI channel 30. */
3646 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */
3647 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */
3648 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */
3650 /* Bit 29 : Disable PPI channel 29. */
3653 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */
3654 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */
3655 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */
3657 /* Bit 28 : Disable PPI channel 28. */
3660 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */
3661 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */
3662 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */
3664 /* Bit 27 : Disable PPI channel 27. */
3667 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */
3668 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */
3669 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */
3671 /* Bit 26 : Disable PPI channel 26. */
3674 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */
3675 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */
3676 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */
3678 /* Bit 25 : Disable PPI channel 25. */
3681 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */
3682 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */
3683 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */
3685 /* Bit 24 : Disable PPI channel 24. */
3688 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */
3689 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */
3690 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */
3692 /* Bit 23 : Disable PPI channel 23. */
3695 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */
3696 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */
3697 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */
3699 /* Bit 22 : Disable PPI channel 22. */
3702 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */
3703 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */
3704 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */
3706 /* Bit 21 : Disable PPI channel 21. */
3709 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */
3710 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */
3711 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */
3713 /* Bit 20 : Disable PPI channel 20. */
3716 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */
3717 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */
3718 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */
3720 /* Bit 15 : Disable PPI channel 15. */
3723 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */
3724 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */
3725 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */
3727 /* Bit 14 : Disable PPI channel 14. */
3730 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */
3731 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */
3732 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */
3734 /* Bit 13 : Disable PPI channel 13. */
3737 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */
3738 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */
3739 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */
3741 /* Bit 12 : Disable PPI channel 12. */
3744 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */
3745 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */
3746 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */
3748 /* Bit 11 : Disable PPI channel 11. */
3751 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */
3752 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */
3753 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */
3755 /* Bit 10 : Disable PPI channel 10. */
3758 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */
3759 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */
3760 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */
3762 /* Bit 9 : Disable PPI channel 9. */
3765 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */
3766 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */
3767 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */
3769 /* Bit 8 : Disable PPI channel 8. */
3772 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */
3773 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */
3774 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */
3776 /* Bit 7 : Disable PPI channel 7. */
3779 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */
3780 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */
3781 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */
3783 /* Bit 6 : Disable PPI channel 6. */
3786 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */
3787 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */
3788 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */
3790 /* Bit 5 : Disable PPI channel 5. */
3793 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */
3794 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */
3795 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */
3797 /* Bit 4 : Disable PPI channel 4. */
3800 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */
3801 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */
3802 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */
3804 /* Bit 3 : Disable PPI channel 3. */
3807 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */
3808 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */
3809 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */
3811 /* Bit 2 : Disable PPI channel 2. */
3814 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */
3815 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */
3816 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */
3818 /* Bit 1 : Disable PPI channel 1. */
3821 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */
3822 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */
3823 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */
3825 /* Bit 0 : Disable PPI channel 0. */
3828 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */
3829 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */
3830 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */
3833 /* Description: Channel group configuration. */
3835 /* Bit 31 : Include CH31 in channel group. */
3838 #define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */
3839 #define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */
3841 /* Bit 30 : Include CH30 in channel group. */
3844 #define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */
3845 #define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */
3847 /* Bit 29 : Include CH29 in channel group. */
3850 #define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */
3851 #define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */
3853 /* Bit 28 : Include CH28 in channel group. */
3856 #define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */
3857 #define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */
3859 /* Bit 27 : Include CH27 in channel group. */
3862 #define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */
3863 #define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */
3865 /* Bit 26 : Include CH26 in channel group. */
3868 #define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */
3869 #define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */
3871 /* Bit 25 : Include CH25 in channel group. */
3874 #define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */
3875 #define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */
3877 /* Bit 24 : Include CH24 in channel group. */
3880 #define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */
3881 #define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */
3883 /* Bit 23 : Include CH23 in channel group. */
3886 #define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */
3887 #define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */
3889 /* Bit 22 : Include CH22 in channel group. */
3892 #define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */
3893 #define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */
3895 /* Bit 21 : Include CH21 in channel group. */
3898 #define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */
3899 #define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */
3901 /* Bit 20 : Include CH20 in channel group. */
3904 #define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */
3905 #define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */
3907 /* Bit 15 : Include CH15 in channel group. */
3910 #define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */
3911 #define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */
3913 /* Bit 14 : Include CH14 in channel group. */
3916 #define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */
3917 #define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */
3919 /* Bit 13 : Include CH13 in channel group. */
3922 #define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */
3923 #define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */
3925 /* Bit 12 : Include CH12 in channel group. */
3928 #define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */
3929 #define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */
3931 /* Bit 11 : Include CH11 in channel group. */
3934 #define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */
3935 #define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */
3937 /* Bit 10 : Include CH10 in channel group. */
3940 #define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */
3941 #define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */
3943 /* Bit 9 : Include CH9 in channel group. */
3946 #define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */
3947 #define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */
3949 /* Bit 8 : Include CH8 in channel group. */
3952 #define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */
3953 #define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */
3955 /* Bit 7 : Include CH7 in channel group. */
3958 #define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */
3959 #define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */
3961 /* Bit 6 : Include CH6 in channel group. */
3964 #define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */
3965 #define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */
3967 /* Bit 5 : Include CH5 in channel group. */
3970 #define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */
3971 #define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */
3973 /* Bit 4 : Include CH4 in channel group. */
3976 #define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */
3977 #define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */
3979 /* Bit 3 : Include CH3 in channel group. */
3982 #define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */
3983 #define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */
3985 /* Bit 2 : Include CH2 in channel group. */
3988 #define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */
3989 #define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */
3991 /* Bit 1 : Include CH1 in channel group. */
3994 #define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */
3995 #define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */
3997 /* Bit 0 : Include CH0 in channel group. */
4000 #define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */
4001 #define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */
4384 /* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decisi…