| /XiangShan/src/main/scala/xiangshan/mem/mdp/ |
| H A D | WaitTable.scala | 39 val update = Input(new MemPredUpdateReq) // RegNext should be added outside constant
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| H A D | StoreSet.scala | 61 val update = Input(new MemPredUpdateReq) // RegNext should be added outside constant
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| /XiangShan/src/main/scala/xiangshan/frontend/ |
| H A D | FrontendBundle.scala | 265 def update(br_valids: Vec[Bool], real_taken_mask: Vec[Bool]): GlobalHistory method
271 def update(shift: UInt, taken: Bool, hist: UInt = this.predHist): ShiftingGlobalHistory = { method
277 def update(br_valids: Vec[Bool], real_taken_mask: Vec[Bool]): ShiftingGlobalHistory = { method
317 def update(br_valids: Vec[Bool], real_taken_mask: Vec[Bool]): CircularGlobalHistory = method
348 def update(ghr: Vec[Bool], histPtr: CGHPtr, num: Int, taken: Bool): FoldedHistory = { method
354 def update(ob: Vec[Bool], num: Int, taken: Bool): FoldedHistory = { method
470 def update(ghv: Vec[Bool], ptr: CGHPtr, shift: Int, taken: Bool): AllFoldedHistories = { method
477 …def update(afhob: AllAheadFoldedHistoryOldestBits, lastBrNumOH: UInt, shift: Int, taken: Bool): Al… method
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| H A D | Bim.scala | 65 val update = RegNext(io.update.bits) constant
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| H A D | SC.scala | 70 val update = Input(new SCUpdate(ctrBits)) constant
213 def update(cause: Bool): SCThreshold = { method
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| H A D | ITTAGE.scala | 127 val update = Input(new ITTageUpdate) constant
207 val update = Input(new ITTageUpdate) constant
475 val update = Wire(new BranchPredictionUpdate) constant
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| H A D | RAS.scala | 97 def update(recover: Bool)(do_push: Bool, do_pop: Bool, do_alloc_new: Bool, method
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| H A D | Tage.scala | 261 val update = Input(new TageUpdate) constant
684 val update = Wire(new BranchPredictionUpdate) constant
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| H A D | newRAS.scala | 729 val update = Wire(new BranchPredictionUpdate) constant
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| H A D | NewFtq.scala | 201 val update = Valid(new BranchPredictionUpdate) constant
1484 val update = io.toBpu.update.bits constant
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| H A D | FTB.scala | 744 val update = Wire(new BranchPredictionUpdate) constant
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| H A D | BPU.scala | 167 val update = Flipped(Valid(new BranchPredictionUpdate)) constant
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| /XiangShan/src/main/scala/xiangshan/cache/wpu/ |
| H A D | VictimList.scala | 50 val update = Vec(nPorts, new WayConflictUpdIO) constant
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| H A D | WPU.scala | 15 def update(vaddr: UInt, data: T ,en: Bool) method
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| /XiangShan/src/main/scala/xiangshan/frontend/icache/ |
| H A D | WayLookup.scala | 67 val update: Valid[ICacheMissResp] = Flipped(ValidIO(new ICacheMissResp)) constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/ |
| H A D | Uncache.scala | 87 def update(x: UncacheWordReq): Unit = { method
99 def update(x: TLBundleD): Unit = { method
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| /XiangShan/src/main/scala/xiangshan/mem/prefetch/ |
| H A D | L1StridePrefetcher.scala | 82 def update(vaddr: UInt, always_update_pre_vaddr: Bool) = { method
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| H A D | SMSPrefetcher.scala | 194 val update = s1_hit && s1_match_vec(i) constant
423 val update = s1_update_mask(i) && s1_update constant
1067 val update = s1_valid && s1_hit && s1_update_vec(i) constant
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| H A D | L1StreamPrefetcher.scala | 94 def update(update_bit_vec: UInt, update_active: Bool) = { method
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| H A D | L1PrefetchComponent.scala | 283 def update(update_bit_vec: UInt, update_sink: UInt) = { method
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| /XiangShan/src/main/scala/xiangshan/cache/ |
| H A D | CacheInstruction.scala | 132 val update = new DistributedCSRUpdateReq constant
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| /XiangShan/src/main/scala/xiangshan/backend/decode/ |
| H A D | FusionDecoder.scala | 519 def update(cs: DecodedInst): Unit = { method
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