| /XiangShan/src/main/scala/utils/ |
| H A D | OverrideableQueue.scala | 11 val entries = Seq.fill(n){ Reg(gen) } constant
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| /XiangShan/src/main/scala/xiangshan/frontend/icache/ |
| H A D | FIFO.scala | 32 val entries: Int, constant
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| /XiangShan/src/main/scala/xiangshan/mem/vector/ |
| H A D | VfofBuffer.scala | 41 val entries = RegInit(0.U.asTypeOf(new VfofDataBundle())) constant
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| H A D | VMergeBuffer.scala | 123 val entries = Reg(Vec(uopSize, new MBufferBundle)) constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/ |
| H A D | Probe.scala | 165 val entries = (0 until cfg.nProbeEntries) map { i => constant
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| H A D | WritebackQueue.scala | 347 val entries = Seq.fill(cfg.nReleaseEntries)(Module(new WritebackEntry(edge))) constant
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| H A D | MissQueue.scala | 961 val entries = Seq.fill(cfg.nMissEntries)(Module(new MissEntry(edge, reqNum))) constant
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| /XiangShan/src/main/scala/xiangshan/cache/mmu/ |
| H A D | TLBStorage.scala | 101 val entries = Reg(Vec(nWays, new TlbSectorEntry(normalPage, superPage))) constant
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| H A D | BitmapCheck.scala | 109 val entries = Reg(Vec(l2tlbParams.llptwsize+2, new bitmapEntry())) constant
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| H A D | TLB.scala | 227 val entries = Module(new TlbStorageWrapper(Width, q, nRespDups)) constant
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| H A D | PageTableWalker.scala | 715 val entries = RegInit(VecInit(Seq.fill(l2tlbParams.llptwsize)(0.U.asTypeOf(new LLPTWEntry())))) constant
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| H A D | MMUBundle.scala | 1019 val entries = new PtwEntries(num, tagLen, level, hasPerm, ReservedBits) constant
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| /XiangShan/src/main/scala/xiangshan/mem/prefetch/ |
| H A D | FDP.scala | 83 val entries = RegInit(VecInit(Seq.fill(SIZE){ (0.U.asTypeOf(new CounterFilterDataBundle())) })) constant
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| H A D | SMSPrefetcher.scala | 316 val entries = Seq.fill(smsParams.active_gen_table_size){ Reg(new AGTEntry()) } constant
931 val entries = Seq.fill(smsParams.pf_filter_size){ Reg(new PrefetchFilterEntry()) } constant
1140 …val entries = RegInit(VecInit(Seq.fill(smsParams.train_filter_size){ (0.U.asTypeOf(new PrefetchReq… constant
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| H A D | L1PrefetchComponent.scala | 173 val entries = Reg(Vec(size, new PrefetchReqBundle)) constant
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| /XiangShan/src/main/scala/xiangshan/mem/lsqueue/ |
| H A D | LoadQueueUncache.scala | 304 val entries = Seq.tabulate(LoadUncacheBufferSize)(i => Module(new UncacheEntry(i))) constant
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| /XiangShan/src/main/scala/xiangshan/backend/issue/ |
| H A D | Entries.scala | 78 val entries = Wire(Vec(params.numEntries, ValidIO(new EntryBundle))) constant
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| H A D | IssueQueue.scala | 122 val entries = Module(new Entries) constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/ |
| H A D | Uncache.scala | 234 val entries = Reg(Vec(UncacheBufferSize, new UncacheEntry)) constant
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