| /XiangShan/src/main/scala/utils/ |
| H A D | PipeWithFlush.scala | 28 val enq = Input(Valid(gen)) constant
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| /XiangShan/src/main/scala/xiangshan/backend/rob/ |
| H A D | RobEnqPtrWrapper.scala | 44 val enq = Vec(RenameWidth, Input(Bool())) constant
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| H A D | ExceptionGen.scala | 41 val enq = Vec(RenameWidth, Flipped(ValidIO(new RobExceptionInfo))) constant
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| H A D | Rob.scala | 68 val enq = new RobEnqIO constant
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| /XiangShan/src/main/scala/xiangshan/mem/sbuffer/ |
| H A D | DatamoduleResultBuffer.scala | 33 val enq = Vec(EnsbufferWidth, Flipped(DecoupledIO(gen))) constant
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| /XiangShan/src/main/scala/xiangshan/backend/issue/ |
| H A D | NewAgeDetector.scala | 28 val enq = Vec(numEnq, Input(Bool())) constant
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| H A D | MultiWakeupQueue.scala | 21 val enq = Flipped(Valid(new EnqBundle)) constant
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| H A D | AgeDetector.scala | 31 val enq = Vec(numEnq, Input(UInt(numEntries.W))) constant
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| H A D | Entries.scala | 521 val enq = Vec(params.numEnq, Flipped(ValidIO(new EntryBundle))) constant
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| H A D | EntryBundles.scala | 101 val enq = Flipped(ValidIO(new EntryBundle)) constant
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| H A D | IssueQueue.scala | 50 val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst))) constant
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| /XiangShan/src/main/scala/xiangshan/frontend/icache/ |
| H A D | FIFO.scala | 25 val enq: DecoupledIO[T] = Flipped(DecoupledIO(gen)) constant
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| /XiangShan/src/main/scala/xiangshan/backend/rename/ |
| H A D | Snapshot.scala | 30 val enq = Input(Bool()) constant
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| /XiangShan/src/main/scala/xiangshan/mem/lsqueue/ |
| H A D | LSQWrapper.scala | 73 val enq = new LsqEnqIO constant
323 val enq = new LsqEnqIO constant
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| H A D | VirtualLoadQueue.scala | 45 val enq = new LqEnqIO constant
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| H A D | LoadMisalignBuffer.scala | 119 val enq = Vec(enqPortNum, Flipped(new MisalignBufferEnqIO)) constant
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| H A D | LoadQueue.scala | 163 val enq = new LqEnqIO constant
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| H A D | StoreMisalignBuffer.scala | 99 val enq = Vec(enqPortNum, Flipped(new MisalignBufferEnqIO)) constant
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| H A D | LoadQueueReplay.scala | 96 val enq = Vec(numEnq, Input(UInt(numEntries.W))) constant
183 val enq = Vec(LoadPipelineWidth, Flipped(Decoupled(new LqWriteBundle))) constant
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| H A D | StoreQueue.scala | 165 val enq = new SqEnqIO constant
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| /XiangShan/src/main/scala/device/ |
| H A D | MemEncrypt.scala | 54 val enq = Flipped(DecoupledIO(new Bundle { constant
352 val enq = Flipped(DecoupledIO(new Bundle { constant
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| H A D | MemEncryptUtil.scala | 30 val enq = Flipped(Irrevocable(gen)) constant
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| /XiangShan/src/main/scala/xiangshan/backend/decode/ |
| H A D | DecodeUnit.scala | 788 val enq = new DecodeUnitEnqIO constant
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| /XiangShan/src/main/scala/xiangshan/frontend/ |
| H A D | NewFtq.scala | 1597 val enq = io.fromBpu.resp constant
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