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Searched defs:enable (Results 1 – 18 of 18) sorted by relevance

/XiangShan/src/main/scala/xiangshan/mem/prefetch/
H A DPrefetcherMonitor.scala30 val enable = Bool() constant
55 val enable = RegInit(true.B) constant
H A DBasePrefecher.scala71 val enable = Input(Bool()) constant
H A DL1PrefetchComponent.scala155 val enable = Input(Bool()) constant
369 val enable = Input(Bool()) constant
857 val enable = io.enable constant
H A DL1StridePrefetcher.scala114 val enable = Input(Bool()) constant
H A DL1StreamPrefetcher.scala165 val enable = Input(Bool()) constant
/XiangShan/src/main/scala/device/
H A DRocketDebugWrapper.scala110 val enable = IO(Input(Bool())) constant
H A DAXI4Plic.scala124 val enable = List.fill(numCores)(List.fill(nrIntrWord)(RegInit(0.U(32.W)))) constant
H A DAXI4Memory.scala82 val enable = IO(Input(Bool())) constant
/XiangShan/src/main/scala/xiangshan/transforms/
H A DPrintControl.scala137 val enable = enableList.isEmpty || inRange(enableList) constant
/XiangShan/src/main/scala/xiangshan/backend/trace/
H A DInterface.scala35 val enable = Bool() constant
41 val enable = Bool() constant
/XiangShan/src/main/scala/xiangshan/frontend/icache/
H A DICacheCtrlUnit.scala116 val enable: Bool = Bool() // enable ECC constant
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/
H A DStorePrefetchBursts.scala160 val enable = Input(Bool()) constant
/XiangShan/src/main/scala/xiangshan/cache/mmu/
H A DL2TLB.scala845 val enable = Input(Bool()) constant
867 val enable = IO(Input(Bool())) constant
H A DTLB.scala274 val enable = portTranslateEnable(i) constant
/XiangShan/src/main/scala/top/
H A DTop.scala279 val enable = Bool() constant
H A DXSNoCTop.scala163 val enable = Bool() constant
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/
H A DInterruptFilter.scala618 val enable = Bool() constant
/XiangShan/src/main/scala/xiangshan/cache/dcache/
H A DDCacheWrapper.scala1725 val enable = IO(Input(Bool())) constant