Fix the csi fuzzer CIR:
Due to FPGA implementation, there CIR actually is [1, 0, c1, c2], not [1, c1, c2]

Fix the csi fuzzer CIR:
Due to FPGA implementation, there CIR actually is [1, 0, c1, c2], not [1, c1, c2]

Add new CSI fuzzer work into app note.

add discussion 344 to iq app note

add discussion 344 to csi radar app note

Add discussions 344 to csi app note.

Also put the demo photo at the beginning of
> radar-self-csi.md

Add cross link to csi radar in csi.md

Update figures for radar-self-csi.md

Improve radar-self-csi.md with waterfall

Update addr2 read-back register

Add FPGA internal loopback inline.

Correct link of owfuzz Vulnerabilities

Update detailed HLS paper link

Add FCCM2023 poster to app note.

Add Thijs HLS FCCM2023 paper to the app note.

Add High-Level Synthesis application note

Update radar-self-csi.md with needed missing command

While changing fft_win_shift 1-->0 not touching bit [9:4]:
They are for equalizer monitor auto-rst: small_eq_out_counter_th

Make set_lbt_th.sh output more human friendly:
While no argument is given (for checking)

Update docs for ADI kuiper (our notter release)

Add ack rx control into the doc

Update iq.md

Sdrpi (#211)

Add sdrpi support

Update packet-iq-self-loopback-test.md