yunsuan - OpenGrok history log for /XiangShan/yunsuan

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5d7351aa	13-Sep-2023	xiaofeibao-xjtu <[email protected]>	bump yunsuan /XiangShan/src/main/scala/utils/PerfCounterUtils.scala /XiangShan/src/main/scala/utils/PipeWithFlush.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/NewPipelineConnect.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WakeUpConfig.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/MultiWakeupQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/xiangshan/backend/issue/MultiWakeupQueueMain.scala /XiangShan/src/test/scala/xiangshan/utils/GenPipeWithFlush.scala /XiangShan/yunsuan
a377bff5	02-Sep-2023	xiaofeibao-xjtu <[email protected]>	bump yunsuan /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgtu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ImmExtractor.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
44d9e45f	21-Aug-2023	xiaofeibao-xjtu <[email protected]>	bump yunsuan /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecNonPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/yunsuan
af6f0420	17-Aug-2023	xiaofeibao-xjtu <[email protected]>	bump yunsuan /XiangShan/.mill-version /XiangShan/Makefile /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/huancun /XiangShan/rocket-chip /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/BusPerfMonitor.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/BundleUtils.scala /XiangShan/src/main/scala/utils/MathUtils.scala /XiangShan/src/main/scala/utils/OptionWrapper.scala /XiangShan/src/main/scala/utils/PerfCounterUtils.scala /XiangShan/src/main/scala/utils/SeqUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/DbEntry.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/LsInfo.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataSource.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RdConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WakeUpConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiterParams.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbConfig.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/predecode/predecode.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/CancelNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/MultiWakeupQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/NewAgeDetector.scala /XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/PregParams.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/CompressUnit.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Snapshot.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/wpu/VictimList.scala /XiangShan/src/main/scala/xiangshan/cache/wpu/WPU.scala /XiangShan/src/main/scala/xiangshan/cache/wpu/WPUWrapper.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/FreeList.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/cache/WpuTest.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/src/test/scala/xiangshan/DecodeTest.scala /XiangShan/src/test/scala/xiangshan/XSTester.scala /XiangShan/src/test/scala/xiangshan/backend/BackendMain.scala /XiangShan/utility /XiangShan/yunsuan
77f7e1dc	20-Jul-2023	xiaofeibao-xjtu <[email protected]>	bump yunsuan /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecNonPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala /XiangShan/yunsuan
dffa5fca	14-Jul-2023	xiaofeibao-xjtu <[email protected]>	bump yunsuan /XiangShan/Makefile /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
3cd2aedb	03-Jul-2023	xiaofeibao-xjtu <[email protected]>	bump yunsuan /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbFuBusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/yunsuan
8552f2d1	26-Jun-2023	xgkiri <[email protected]>	update submodule 'yunsuan' /XiangShan/Makefile /XiangShan/difftest /XiangShan/huancun /XiangShan/src/main/scala/utils/MapUtils.scala /XiangShan/src/main/scala/utils/OptionWrapper.scala /XiangShan/src/main/scala/utils/PipeWithFlush.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/NewPipelineConnect.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RdConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WakeUpConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiterParams.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbFuBusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/utils/VecDataSplitModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala /XiangShan/src/main/scala/xiangshan/backend/issue/FuBusyTableRead.scala /XiangShan/src/main/scala/xiangshan/backend/issue/FuBusyTableWrite.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/MultiWakeupQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/xiangshan/backend/issue/MultiWakeupQueueMain.scala /XiangShan/src/test/scala/xiangshan/utils/GenPipeWithFlush.scala /XiangShan/utility /XiangShan/yunsuan
642a6c5b	26-May-2023	Xuan Hu <[email protected]>	bump yunsuan /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/ByteMaskTailGen.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Utils.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecSrcTypeModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/utils/MaskExtrator.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/utils/UIntToCont0s.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/utils/UIntToCont1s.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/utils/VecDataSplitModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBankedArray.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/FreeList.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/src/test/scala/xiangshan/backend/fu/vector/ByteMaskTailGenTest.scala /XiangShan/utility /XiangShan/yunsuan
bf50c572	23-May-2023	Xuan Hu <[email protected]>	bump yunsuan /XiangShan/rocket-chip /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Utils.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/utils/ScalaDupToVector.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ImmExtractor.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/yunsuan
414fe7eb	22-May-2023	Xuan Hu <[email protected]>	bump yunsuan /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComplex.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Utils.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VFPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIMacU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPerm.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/MulUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
3f6c8c2c	10-May-2023	Xuan Hu <[email protected]>	Merge branch 'dev-vector' into new-backend /XiangShan/build.sc /XiangShan/src/main/resources/espresso /XiangShan/src/main/scala/utils/NamedUInt.scala /XiangShan/src/main/scala/utils/OptionWrapper.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComplex.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Bku.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VFPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIMacU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPerm.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/DivUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/MulUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ImmExtractor.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/WakeupQueue.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/RefCounter.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/xiangshan/backend/fu/VsetModuleMain.scala /XiangShan/src/test/scala/xiangshan/backend/fu/VsetRef.scala /XiangShan/src/test/scala/xiangshan/backend/fu/VsetTop.scala /XiangShan/yunsuan
adf68ff3	05-May-2023	czw <[email protected]>	func(UopDivType): support vcompress & some insts of VIMac (#2067) func(UopDivType): support UopDivType.VEC_COMPRESS & vcompress test pass func(VIMac): add VIMac pom(yunsuan): add VimacType * fu func(UopDivType): support vcompress & some insts of VIMac (#2067) func(UopDivType): support UopDivType.VEC_COMPRESS & vcompress test pass func(VIMac): add VIMac pom(yunsuan): add VimacType * func(UopDivType): support UopDivType.VEC_COMPRESS & vcompress test pass * func(VIMac): add VIMac 1. support for vmul/vmvmulh/vmvmulhu/vmvmulhsu 2. support for vmacc/vnmsac/vmadd/vnmsub * pom(yunsuan): add VimacType show more ... /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComplex.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIMacU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPerm.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
8e7e08fc	28-Apr-2023	fdy <[email protected]>	bump yunsuan /XiangShan/.gitignore /XiangShan/Makefile /XiangShan/Makefile.test /XiangShan/build.sc /XiangShan/debug/local_ci.py /XiangShan/difftest /XiangShan/ready-to-run /XiangShan/scripts/constantHelper.py /XiangShan/scripts/gen_sep_mem.sh /XiangShan/scripts/top-down/README.md /XiangShan/scripts/top-down/top-down.sh /XiangShan/scripts/top-down/top_down.py /XiangShan/scripts/utils/convert.sh /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Generator.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/ArbiterHelper.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/OverrideableQueue.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/DbEntry.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/MemCtrl.scala /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RdConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiterParams.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbConfig.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Bku.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Branch.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/DivUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/MulUnit.scala /XiangShan/src/main/scala/xiangshan/backend/issue/AgeDetector.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DeqPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ImmExtractor.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/PregParams.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/RefCounter.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWPU.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/MemTrace.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchInterface.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/vector/MemVectorInterface.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/fu/IntDiv.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/src/test/scala/xiangshan/DecodeTest.scala /XiangShan/src/test/scala/xiangshan/XSTester.scala /XiangShan/src/test/scala/xiangshan/backend/BackendMain.scala /XiangShan/src/test/scala/xiangshan/backend/DataPathMain.scala /XiangShan/src/test/scala/xiangshan/backend/SchedulerMain.scala /XiangShan/src/test/scala/xiangshan/backend/dispatch/Dispatch2IqMain.scala /XiangShan/src/test/scala/xiangshan/backend/issue/DataArrayMain.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueMain.scala /XiangShan/src/test/scala/xiangshan/backend/issue/StatusArrayMain.scala /XiangShan/utility /XiangShan/yunsuan
8a6bae41	24-Apr-2023	czw <[email protected]>	pom(yunsuan): add IALU V5 & fix some bugs 1. func(IALU): add IALU V5 2. fix(VIntMisc64b): fix a bug in VIntMisc64b 3. fix(vrgather): fix a bug that the value of vrgather_vd depends on ma /XiangShan/ready-to-run /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VFPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPerm.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
e0940d36	14-Apr-2023	czw <[email protected]>	pom(yunsuan): fix some bugs about VMask & add IALU V4 /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
8c1425d9	11-Apr-2023	czw <[email protected]>	pom(yunsuan): add some test & fix some bugs 1. add Vector Idiv module 2. fix(package): fix bug that dummy and vnclip_wv encoding conflicts 3. fix(VialuFixType): fix a bug that vnclip_wv should be si pom(yunsuan): add some test & fix some bugs 1. add Vector Idiv module 2. fix(package): fix bug that dummy and vnclip_wv encoding conflicts 3. fix(VialuFixType): fix a bug that vnclip_wv should be sign show more ... /XiangShan/build.sc /XiangShan/rocket-chip /XiangShan/src/main/resources/espresso /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
1d2facad	07-Apr-2023	xiaofeibao-xjtu <[email protected]>	bump yunsuan, func(vfalu): fix positive and negative zero bug /XiangShan/yunsuan
fbc24a91	05-Apr-2023	czw <[email protected]>	func(UopDivType): support VEC_SLIDEUP/VEC_ISLIDEUP/VEC_SLIDEDOWN/VEC_ISLIDEDOWN (#2028) * func(UopDivType): support VEC_SLIDEUP/VEC_ISLIDEUP/VEC_SLIDEDOWN/VEC_ISLIDEDOWN * pom(yunsuan): add isVsild func(UopDivType): support VEC_SLIDEUP/VEC_ISLIDEUP/VEC_SLIDEDOWN/VEC_ISLIDEDOWN (#2028) * func(UopDivType): support VEC_SLIDEUP/VEC_ISLIDEUP/VEC_SLIDEDOWN/VEC_ISLIDEDOWN * pom(yunsuan): add isVsilde in VpermType & fix bugs of Permutation show more ... /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VFPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPerm.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
52abbe6e	03-Apr-2023	xiaofeibao-xjtu <[email protected]>	bump yunsuan, add VfpuType /XiangShan/yunsuan
b8298242	02-Apr-2023	czw <[email protected]>	func(DecodeUnitComp): support VEC_VRED (#2017) * func(DecodeUnitComp): support VEC_VRED of UopDivType * fix(vxsat):fix bug that VPU's vxsat shout be arbitrated * pom(yunsuan):fix Decode of vmvsx & func(DecodeUnitComp): support VEC_VRED (#2017) * func(DecodeUnitComp): support VEC_VRED of UopDivType * fix(vxsat):fix bug that VPU's vxsat shout be arbitrated * pom(yunsuan):fix Decode of vmvsx & add some test for VPERM show more ... /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VFPU.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
35418604	31-Mar-2023	xiaofeibao-xjtu <[email protected]>	bump yunsuan, support vfdiv.vv vfdiv.vf vfrdiv.fv /XiangShan/yunsuan
4365a7a7	31-Mar-2023	czw <[email protected]>	func(DecodeUnitComp) : support vfslide1up & vslide1down & vfslide1down (#2012) * func(DecodeUnitComp): support vfslide1up.vf * func(DecodeUnitComp):support vslide1down & vfslide1down * pom(yunsuan func(DecodeUnitComp) : support vfslide1up & vslide1down & vfslide1down (#2012) * func(DecodeUnitComp): support vfslide1up.vf * func(DecodeUnitComp):support vslide1down & vfslide1down * pom(yunsuan):add vfslide1up & vfslide1down 1. func(VFMA):add vfmsac, vfnmsac, vfmadd, vfnmadd, vfmsub, vfnmsub, vfwmul, vfwmacc, vfwnmacc, vfwmsac, vfwnmsac and their test supports 2. func(VpermType): add vfslide1up & vfslide1down show more ... /XiangShan/ready-to-run /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VFPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPerm.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
de9e1949	28-Mar-2023	czw <[email protected]>	pom(yunsuan): add IALU V3 (#2004) 1. func(VPERM): fix tail process, optimize vcompress, change vslide module name 2. func(VPERM): change to 2-stage 3. test(VPERM): add golden model and test: vslid pom(yunsuan): add IALU V3 (#2004) 1. func(VPERM): fix tail process, optimize vcompress, change vslide module name 2. func(VPERM): change to 2-stage 3. test(VPERM): add golden model and test: vslidedown 4. test(VPERM): set vxsat=0 for vperm 5. test(VFADD): support vector-scalar operations func(VFADD): support vector-scalar operations 6. test: include 7. func(VFMA): add input:op_code,frs1,is_frs1; support vfmul.vv 8. func(VFMA):add vfmul.vf vfnmacc.vv vfnmacc.vf and their test supports 9. func(IALU):add IALU V3 * fix(decode): fix decode bug of selImm 1. fix decode bug of selImm 2. change VipuType to VpermType * func(yunsuan): add VIAlu code v3 1. add VIAlu code v3 2. Update the IO of VFPU * pom(yunsuan): add IALU V3 1. func(VPERM): fix tail process, optimize vcompress, change vslide module name 2. func(VPERM): change to 2-stage 3. test(VPERM): add golden model and test: vslidedown 4. test(VPERM): set vxsat=0 for vperm 5. test(VFADD): support vector-scalar operations func(VFADD): support vector-scalar operations 6. test: include <algorithm> 7. func(VFMA): add input:op_code,frs1,is_frs1; support vfmul.vv 8. func(VFMA):add vfmul.vf vfnmacc.vv vfnmacc.vf and their test supports 9. func(IALU):add IALU V3 show more ... /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VFPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPerm.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
3f9db32a	24-Mar-2023	czw <[email protected]>	pom(yunsuan):fix some bug & add test for VIntFixpAlu (#1997) 1. pom(build.sbt):Update the version of scala in sbt 2. func(VIntFixpAlu):add test for VIntFixpAlu 3. fix(vand): fix vand OPType 4. fi pom(yunsuan):fix some bug & add test for VIntFixpAlu (#1997) 1. pom(build.sbt):Update the version of scala in sbt 2. func(VIntFixpAlu):add test for VIntFixpAlu 3. fix(vand): fix vand OPType 4. fix(VIntAdder64b):fix a bug that mask inst result should be 1 when !vm && !vmask(i) show more ... /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VFPU.scala /XiangShan/yunsuan
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