style(DebugModule): remove unnecessary `XSDebugModuleParams` (#4155)

It is more straight-forward to use `DebugModuleParams` in `Config.scala`.

fix(rob): fix needflush when rob has redirect (#4153)

* This PR fix the boundary case where rob has redirect.
* The `needflush` signal should be `true` when rob flushes all entries.

Co-authored-by:

fix(rob): fix needflush when rob has redirect (#4153)

* This PR fix the boundary case where rob has redirect.
* The `needflush` signal should be `true` when rob flushes all entries.

Co-authored-by: xiaofeibao-xjtu <[email protected]>

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fix(XSTop): assign unique nodeID to each core (#4151)

Without this commit, CHI messages cannot be correctly routed in
multi-core scenarios, leading to simulation errors.

fix(uncache): consider both corrupt and denied when granting (#4150)

From TileLink SPEC 1.9.3 Chapter7 "TileLink Uncached Lightweight
(TL-UL)":

* AccessAck: `d_corrupt` is reserved and must be 0.
*

fix(uncache): consider both corrupt and denied when granting (#4150)

From TileLink SPEC 1.9.3 Chapter7 "TileLink Uncached Lightweight
(TL-UL)":

* AccessAck: `d_corrupt` is reserved and must be 0.
* AccessAckData, `d_corrupt` being HIGH indicates that masked data in
this beat is corrupt.

So it need consider both `d_denied` and `d_corrupt` when geting the
data.

For uncache now, it complete in one beat, so there can execute `d_denied
|| d_corrupt` directly.

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fix(LoadUnit): `fast replay` no longer requests to `RAR/RAW Queue` (#4149)

For `fast replay`, there is no need to request access to the `RAW/RAW
Queue`.
This prevents the `RAW Queue` from constantly

fix(LoadUnit): `fast replay` no longer requests to `RAR/RAW Queue` (#4149)

For `fast replay`, there is no need to request access to the `RAW/RAW
Queue`.
This prevents the `RAW Queue` from constantly ping-ponging between `not
full/full` due to `revoke`.

These two lines were removed because it would lead to combinatorial
logic loops and it was an unwanted condition:

https://github.com/OpenXiangShan/XiangShan/blob/dfc474ebe17bbfb1bf2ec4cc122301a9c7998e09/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala#L1269-L1270

---

**This may result in some performance gains.**

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style(LoadUnit): removes redundant 'fast_rep_out' assignments (#4148)

feat(DM, hartReset): support `hartReset` which could reset selected harts

* Add hartResetReq in XSNocTop.
* Support `hartReset` features

feat(CSR): set init 0 for htimedelta csr (#4145)

fix(StoreQueue): remove the incorrect redirect logic (#4139)

submodule(CoupledL2): bump CoupledL2 (#4140)

1. https://github.com/OpenXiangShan/CoupledL2/pull/309
2. https://github.com/OpenXiangShan/CoupledL2/pull/312

fix(VLSU): fix vector exception writeback to 'MergeBuffer' logic (#4137)

Fixed the bug of abnormal signal loss when writing back.

Previously, we expected to compare only the ports of the writebacks

fix(VLSU): fix vector exception writeback to 'MergeBuffer' logic (#4137)

Fixed the bug of abnormal signal loss when writing back.

Previously, we expected to compare only the ports of the writebacks that
triggered the exception and pick the oldest.

But amazingly, I just realised that the implementation doesn't match the
annotation. The current implementation can be problematic in that if
the write-back port that did not have an exception is older, the port that
triggered the exception is not elected.

Use s3_exception to try to optimise timing.

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fix(LoadUnit): use `lqIdx` to determine age (#4136)

1. `lqIdx` has less bit width.
2. for vectors, the `robIdx` is the same for multiple `flow`s.
Previously, for vectors, we would additionally use `

fix(LoadUnit): use `lqIdx` to determine age (#4136)

1. `lqIdx` has less bit width.
2. for vectors, the `robIdx` is the same for multiple `flow`s.
Previously, for vectors, we would additionally use `uopIdx` for
judgement. But actually, in theory, we only need to use `lqIdx/sqIdx`.

Here we change the age judgement for vectors to `lqIdx` to ensure
accurate age judgement. And change the age judgement of scalar to
`lqIdx` as well to reduce the cost.

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fix(zvfh): fix zvfh corner case which should support vsew8
* vfwcvtfx,vfwcvtfxu,vfncvtxuf,vfncvtxf,vfncvtrodxuf,vfncvtrodxf should support vsew8

chore(Parameters): add svnapot extension string (#4133)

fix(hideleg): fix the read value of the LCOFI bit of hideleg.

For bits of mideleg that are zero, the corresponding bits in
hideleg, hip, and hie are read-only zeros.

The VSSIP, VSTIP, VSEIP in mide

fix(hideleg): fix the read value of the LCOFI bit of hideleg.

For bits of mideleg that are zero, the corresponding bits in
hideleg, hip, and hie are read-only zeros.

The VSSIP, VSTIP, VSEIP in mideleg are read-only ones
when the H extension is implemented.

When the hypervisor extension is implemented, if a bit is zero in
the same position in both mideleg and mvien, then that bit is
read-only zero in hideleg (in addition to being read-only zero in
sip, sie, hip, and hie). But if a bit for one of interrupts 13-63
is a one in either mideleg or mvien, then the same bit in hideleg
may be writable or may be read-only zero, depending on the
implementation. No bits in hideleg are ever read-only ones. The
RISC-V Privileged Architecture further constrains bits 12:0 of
hideleg.

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timing(CSR): using addr/wdata after 1 cycle for writing frontend and memory (#4119)

Register 1 cycle addr and wdata, then write to frontend and memory.

fix(Rename): fuse lui-load only if `rfWen` of lui is true (#4131)

fix(Unprivileged): wait a cycle to update `time` when `nextV =/= v` (#4132)

fix(exception): width of exception type should be explicitly noted (#4124)

feat(Svnapot): support Svnapot extension (#4107)

area(MainPipe): remove duplicate signals (#4117)

fix(ICacheMissUnit): clear corrupt_r when response is sent to MainPipe (#4112)

fix(redirectGen): fix bug of csr's cfiUpdate (#4118)

submodule(CoupledL2): bump for bop mem check (#4115)

submodule(OpenLLC): add support for top-down analysis (#4113)