xref: /XiangShan/src/main/scala/xiangshan/L2Top.scala (revision ae3969316eb5e8c2cf8f323541ccba5fd8b22c3d) 
1/***************************************************************************************
2  * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3  * Copyright (c) 2020-2021 Peng Cheng Laboratory
4  *
5  * XiangShan is licensed under Mulan PSL v2.
6  * You can use this software according to the terms and conditions of the Mulan PSL v2.
7  * You may obtain a copy of Mulan PSL v2 at:
8  *          http://license.coscl.org.cn/MulanPSL2
9  *
10  * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11  * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12  * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13  *
14  * See the Mulan PSL v2 for more details.
15  ***************************************************************************************/
16
17package xiangshan
18
19import chisel3._
20import chisel3.util._
21import org.chipsalliance.cde.config._
22import chisel3.util.{Valid, ValidIO}
23import freechips.rocketchip.diplomacy._
24import freechips.rocketchip.interrupts._
25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, MaxHartIdBits}
26import freechips.rocketchip.tilelink._
27import coupledL2.{L2ParamKey, EnableCHI}
28import coupledL2.tl2tl.TL2TLCoupledL2
29import coupledL2.tl2chi.{TL2CHICoupledL2, PortIO, CHIIssue}
30import huancun.BankBitsKey
31import system.{HasSoCParameter, SoCParamsKey}
32import top.BusPerfMonitor
33import utility._
34import xiangshan.cache.mmu.TlbRequestIO
35import xiangshan.backend.fu.PMPRespBundle
36import xiangshan.backend.trace.{Itype, TraceCoreInterface}
37
38class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter {
39  val ecc_error = Valid(UInt(soc.PAddrBits.W))
40}
41
42class XSL1BusErrors()(implicit val p: Parameters) extends BusErrors {
43  val icache = new L1BusErrorUnitInfo
44  val dcache = new L1BusErrorUnitInfo
45  val l2 = new L1BusErrorUnitInfo
46
47  override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] =
48    List(
49      Some(icache.ecc_error, "I_ECC", "Icache ecc error"),
50      Some(dcache.ecc_error, "D_ECC", "Dcache ecc error"),
51      Some(l2.ecc_error, "L2_ECC", "L2Cache ecc error")
52    )
53}
54
55/**
56  *   L2Top contains everything between Core and XSTile-IO
57  */
58class L2TopInlined()(implicit p: Parameters) extends LazyModule
59  with HasXSParameter
60  with HasSoCParameter
61{
62  override def shouldBeInlined: Boolean = true
63
64  def chainBuffer(depth: Int, n: String): (Seq[LazyModule], TLNode) = {
65    val buffers = Seq.fill(depth){ LazyModule(new TLBuffer()) }
66    buffers.zipWithIndex.foreach{ case (b, i) => {
67      b.suggestName(s"${n}_${i}")
68    }}
69    val node = buffers.map(_.node.asInstanceOf[TLNode]).reduce(_ :*=* _)
70    (buffers, node)
71  }
72  val enableL2 = coreParams.L2CacheParamsOpt.isDefined
73  // =========== Components ============
74  val l1_xbar = TLXbar()
75  val mmio_xbar = TLXbar()
76  val mmio_port = TLIdentityNode() // to L3
77  val memory_port = if (enableCHI && enableL2) None else Some(TLIdentityNode())
78  val beu = LazyModule(new BusErrorUnit(
79    new XSL1BusErrors(),
80    BusErrorUnitParams(soc.BEURange.base, soc.BEURange.mask.toInt + 1)
81  ))
82
83  val i_mmio_port = TLTempNode()
84  val icachectrl_port_opt = if(icacheParameters.cacheCtrlAddressOpt.nonEmpty) Option(TLTempNode()) else None
85  val d_mmio_port = TLTempNode()
86
87  val misc_l2_pmu = BusPerfMonitor(name = "Misc_L2", enable = !debugOpts.FPGAPlatform) // l1D & l1I & PTW
88  val l2_l3_pmu = BusPerfMonitor(name = "L2_L3", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
89  val xbar_l2_buffer = TLBuffer()
90
91  val enbale_tllog = !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB
92  val l1d_logger = TLLogger(s"L2_L1D_${coreParams.HartId}", enbale_tllog)
93  val l1i_logger = TLLogger(s"L2_L1I_${coreParams.HartId}", enbale_tllog)
94  val ptw_logger = TLLogger(s"L2_PTW_${coreParams.HartId}", enbale_tllog)
95  val ptw_to_l2_buffer = LazyModule(new TLBuffer)
96  val i_mmio_buffer = LazyModule(new TLBuffer)
97
98  val clint_int_node = IntIdentityNode()
99  val debug_int_node = IntIdentityNode()
100  val plic_int_node = IntIdentityNode()
101  val nmi_int_node = IntIdentityNode()
102
103  println(s"enableCHI: ${enableCHI}")
104  val l2cache = if (enableL2) {
105    val config = new Config((_, _, _) => {
106      case L2ParamKey => coreParams.L2CacheParamsOpt.get.copy(
107        hartId = p(XSCoreParamsKey).HartId,
108        PmemRanges = p(SoCParamsKey).PmemRanges,
109        FPGAPlatform = debugOpts.FPGAPlatform
110      )
111      case EnableCHI => p(EnableCHI)
112      case CHIIssue => p(CHIIssue)
113      case BankBitsKey => log2Ceil(coreParams.L2NBanks)
114      case MaxHartIdBits => p(MaxHartIdBits)
115      case LogUtilsOptionsKey => p(LogUtilsOptionsKey)
116      case PerfCounterOptionsKey => p(PerfCounterOptionsKey)
117    })
118    if (enableCHI) Some(LazyModule(new TL2CHICoupledL2()(new Config(config))))
119    else Some(LazyModule(new TL2TLCoupledL2()(new Config(config))))
120  } else None
121  val l2_binder = coreParams.L2CacheParamsOpt.map(_ => BankBinder(coreParams.L2NBanks, 64))
122
123  // =========== Connection ============
124  // l2 to l2_binder, then to memory_port
125  l2cache match {
126    case Some(l2) =>
127      l2_binder.get :*= l2.node :*= xbar_l2_buffer :*= l1_xbar :=* misc_l2_pmu
128      l2 match {
129        case l2: TL2TLCoupledL2 =>
130          memory_port.get := l2_l3_pmu := TLClientsMerger() := TLXbar() :=* l2_binder.get
131        case l2: TL2CHICoupledL2 =>
132          l2.managerNode := TLXbar() :=* l2_binder.get
133          l2.mmioNode := mmio_port
134      }
135    case None =>
136      memory_port.get := l1_xbar
137  }
138
139  mmio_xbar := TLBuffer.chainNode(2) := i_mmio_port
140  mmio_xbar := TLBuffer.chainNode(2) := d_mmio_port
141  beu.node := TLBuffer.chainNode(1) := mmio_xbar
142  if (icacheParameters.cacheCtrlAddressOpt.nonEmpty) {
143    icachectrl_port_opt.get := TLBuffer.chainNode(1) := mmio_xbar
144  }
145
146  // filter out in-core addresses before sent to mmio_port
147  // Option[AddressSet] ++ Option[AddressSet] => List[AddressSet]
148  private def mmioFilters: Seq[AddressSet] =
149    (icacheParameters.cacheCtrlAddressOpt ++ dcacheParameters.cacheCtrlAddressOpt).toSeq
150  mmio_port :=
151    TLFilter(TLFilter.mSubtract(mmioFilters)) :=
152    TLBuffer() :=
153    mmio_xbar
154
155  class Imp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
156    val io = IO(new Bundle {
157      val beu_errors = Input(chiselTypeOf(beu.module.io.errors))
158      val reset_vector = new Bundle {
159        val fromTile = Input(UInt(PAddrBits.W))
160        val toCore = Output(UInt(PAddrBits.W))
161      }
162      val hartId = new Bundle() {
163        val fromTile = Input(UInt(64.W))
164        val toCore = Output(UInt(64.W))
165      }
166      val cpu_halt = new Bundle() {
167        val fromCore = Input(Bool())
168        val toTile = Output(Bool())
169      }
170      val cpu_critical_error = new Bundle() {
171        val fromCore = Input(Bool())
172        val toTile = Output(Bool())
173      }
174      val hartIsInReset = new Bundle() {
175        val resetInFrontend = Input(Bool())
176        val toTile = Output(Bool())
177      }
178      val traceCoreInterface = new Bundle{
179        val fromCore = Flipped(new TraceCoreInterface)
180        val toTile   = new TraceCoreInterface
181      }
182      val debugTopDown = new Bundle() {
183        val robTrueCommit = Input(UInt(64.W))
184        val robHeadPaddr = Flipped(Valid(UInt(36.W)))
185        val l2MissMatch = Output(Bool())
186      }
187      val chi = if (enableCHI) Some(new PortIO) else None
188      val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None
189      val l2_tlb_req = new TlbRequestIO(nRespDups = 2)
190      val l2_pmp_resp = Flipped(new PMPRespBundle)
191      val l2_hint = ValidIO(new L2ToL1Hint())
192      val perfEvents = Output(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent))
193      // val reset_core = IO(Output(Reset()))
194    })
195
196    val resetDelayN = Module(new DelayN(UInt(PAddrBits.W), 5))
197
198    beu.module.io.errors.icache := io.beu_errors.icache
199    beu.module.io.errors.dcache := io.beu_errors.dcache
200    resetDelayN.io.in := io.reset_vector.fromTile
201    io.reset_vector.toCore := resetDelayN.io.out
202    io.hartId.toCore := io.hartId.fromTile
203    io.cpu_halt.toTile := io.cpu_halt.fromCore
204    io.cpu_critical_error.toTile := io.cpu_critical_error.fromCore
205    // trace interface
206    val traceToTile = io.traceCoreInterface.toTile
207    val traceFromCore = io.traceCoreInterface.fromCore
208    traceFromCore.fromEncoder := RegNext(traceToTile.fromEncoder)
209    traceToTile.toEncoder.trap := RegEnable(
210      traceFromCore.toEncoder.trap,
211      traceFromCore.toEncoder.groups(0).valid && Itype.isTrap(traceFromCore.toEncoder.groups(0).bits.itype)
212    )
213    traceToTile.toEncoder.priv := RegEnable(
214      traceFromCore.toEncoder.priv,
215      traceFromCore.toEncoder.groups(0).valid
216    )
217    (0 until TraceGroupNum).foreach{ i =>
218      traceToTile.toEncoder.groups(i).valid := RegNext(traceFromCore.toEncoder.groups(i).valid)
219      traceToTile.toEncoder.groups(i).bits.iretire := RegNext(traceFromCore.toEncoder.groups(i).bits.iretire)
220      traceToTile.toEncoder.groups(i).bits.itype := RegNext(traceFromCore.toEncoder.groups(i).bits.itype)
221      traceToTile.toEncoder.groups(i).bits.ilastsize := RegEnable(
222        traceFromCore.toEncoder.groups(i).bits.ilastsize,
223        traceFromCore.toEncoder.groups(i).valid
224      )
225      traceToTile.toEncoder.groups(i).bits.iaddr := RegEnable(
226        traceFromCore.toEncoder.groups(i).bits.iaddr,
227        traceFromCore.toEncoder.groups(i).valid
228      )
229    }
230
231    dontTouch(io.hartId)
232    dontTouch(io.cpu_halt)
233    dontTouch(io.cpu_critical_error)
234    if (!io.chi.isEmpty) { dontTouch(io.chi.get) }
235
236    val hartIsInReset = RegInit(true.B)
237    hartIsInReset := io.hartIsInReset.resetInFrontend || reset.asBool
238    io.hartIsInReset.toTile := hartIsInReset
239
240    if (l2cache.isDefined) {
241      val l2 = l2cache.get.module
242      io.l2_hint := l2.io.l2_hint
243      l2.io.debugTopDown.robHeadPaddr := DontCare
244      l2.io.hartId := io.hartId.fromTile
245      l2.io.debugTopDown.robHeadPaddr := io.debugTopDown.robHeadPaddr
246      l2.io.debugTopDown.robTrueCommit := io.debugTopDown.robTrueCommit
247      io.debugTopDown.l2MissMatch := l2.io.debugTopDown.l2MissMatch
248
249      /* l2 tlb */
250      io.l2_tlb_req.req.bits := DontCare
251      io.l2_tlb_req.req.valid := l2.io.l2_tlb_req.req.valid
252      io.l2_tlb_req.resp.ready := l2.io.l2_tlb_req.resp.ready
253      io.l2_tlb_req.req.bits.vaddr := l2.io.l2_tlb_req.req.bits.vaddr
254      io.l2_tlb_req.req.bits.cmd := l2.io.l2_tlb_req.req.bits.cmd
255      io.l2_tlb_req.req.bits.size := l2.io.l2_tlb_req.req.bits.size
256      io.l2_tlb_req.req.bits.kill := l2.io.l2_tlb_req.req.bits.kill
257      io.l2_tlb_req.req.bits.no_translate := l2.io.l2_tlb_req.req.bits.no_translate
258      io.l2_tlb_req.req_kill := l2.io.l2_tlb_req.req_kill
259      io.perfEvents := l2.io_perf
260
261      val allPerfEvents = l2.getPerfEvents
262      if (printEventCoding) {
263        for (((name, inc), i) <- allPerfEvents.zipWithIndex) {
264          println("L2 Cache perfEvents Set", name, inc, i)
265        }
266      }
267
268      l2.io.l2_tlb_req.resp.valid := io.l2_tlb_req.resp.valid
269      l2.io.l2_tlb_req.req.ready := io.l2_tlb_req.req.ready
270      l2.io.l2_tlb_req.resp.bits.paddr.head := io.l2_tlb_req.resp.bits.paddr.head
271      l2.io.l2_tlb_req.resp.bits.pbmt := io.l2_tlb_req.resp.bits.pbmt.head
272      l2.io.l2_tlb_req.resp.bits.miss := io.l2_tlb_req.resp.bits.miss
273      l2.io.l2_tlb_req.resp.bits.excp.head.gpf := io.l2_tlb_req.resp.bits.excp.head.gpf
274      l2.io.l2_tlb_req.resp.bits.excp.head.pf := io.l2_tlb_req.resp.bits.excp.head.pf
275      l2.io.l2_tlb_req.resp.bits.excp.head.af := io.l2_tlb_req.resp.bits.excp.head.af
276      l2.io.l2_tlb_req.pmp_resp.ld := io.l2_pmp_resp.ld
277      l2.io.l2_tlb_req.pmp_resp.st := io.l2_pmp_resp.st
278      l2.io.l2_tlb_req.pmp_resp.instr := io.l2_pmp_resp.instr
279      l2.io.l2_tlb_req.pmp_resp.mmio := io.l2_pmp_resp.mmio
280      l2.io.l2_tlb_req.pmp_resp.atomic := io.l2_pmp_resp.atomic
281      l2cache.get match {
282        case l2cache: TL2CHICoupledL2 =>
283          val l2 = l2cache.module
284          l2.io_nodeID := io.nodeID.get
285          io.chi.get <> l2.io_chi
286        case l2cache: TL2TLCoupledL2 =>
287      }
288
289      beu.module.io.errors.l2.ecc_error.valid := l2.io.error.valid
290      beu.module.io.errors.l2.ecc_error.bits := l2.io.error.address
291    } else {
292      io.l2_hint := 0.U.asTypeOf(io.l2_hint)
293      io.debugTopDown <> DontCare
294
295      io.l2_tlb_req.req.valid := false.B
296      io.l2_tlb_req.req.bits := DontCare
297      io.l2_tlb_req.req_kill := DontCare
298      io.l2_tlb_req.resp.ready := true.B
299      io.perfEvents := DontCare
300
301      beu.module.io.errors.l2 := 0.U.asTypeOf(beu.module.io.errors.l2)
302    }
303  }
304
305  lazy val module = new Imp(this)
306}
307
308class L2Top()(implicit p: Parameters) extends LazyModule
309  with HasXSParameter
310  with HasSoCParameter {
311
312  override def shouldBeInlined: Boolean = false
313
314  val inner = LazyModule(new L2TopInlined())
315
316  class Imp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
317    val io = IO(inner.module.io.cloneType)
318    val reset_core = IO(Output(Reset()))
319    io <> inner.module.io
320
321    if (debugOpts.ResetGen) {
322      ResetGen(ResetGenNode(Seq(
323        CellNode(reset_core),
324        ModuleNode(inner.module)
325      )), reset, sim = false)
326    } else {
327      reset_core := DontCare
328    }
329  }
330
331  lazy val module = new Imp(this)
332}