fix(TopDown, frontend): remove frontBubble double count on redirect (#4196)

fix(dret): clear xstatus.xDT conditionally when dret is executed (#4193)

fix(snapshot): fix bug of snptSelect when only flag is diffrent form redirect robidx

fix(PTWCache): avoid X-prop of spRefill (#4195)

In the previous design, the `spRefill` signal will be true when the
`refill.levelOH.sp` or `memPte(0).isNapot(refill.level_dup(0))`
conditions is me

fix(PTWCache): avoid X-prop of spRefill (#4195)

In the previous design, the `spRefill` signal will be true when the
`refill.levelOH.sp` or `memPte(0).isNapot(refill.level_dup(0))`
conditions is met, and acted as a control signal to control the refill
of the sp entries. However, `memPte(0).isNapot(refill.level_dup(0))`
does not determine whether `refill.level_dup(0)` is valid. When
`refill.level_dup(0)` is X, it causes `spRefill` to also be X, which in
turn causes X-prop.

This commit adds `refill.levelOH.l0` to `isNapot`. On the one hand, only
`levelOH.l0` (4KB page) can be a Svnapot page; on the other hand, the
assignment of `refill.levelOH.l0` takes `refill.valid` into account,
thus avoiding X-prop.

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fix(L2TLB): Fix stuck caused by MissQueue full (#4191)

In the previous design, we will ensure that L2 TLB will be able to
receive the request by repeater between L1 TLB and L2 TLB. Specifically,
t

fix(L2TLB): Fix stuck caused by MissQueue full (#4191)

In the previous design, we will ensure that L2 TLB will be able to
receive the request by repeater between L1 TLB and L2 TLB. Specifically,
the number of entries in L2 TLB MissQueue will be greater than or equal
to the sum of itlbRepeater entries + dtlbRepeater entries, so as long as
the repeater is able to accept, the L2 TLB will be able to handle.

However, there is always a problem with this approach: the repeater does
not know whether multiple reqs of the TLB will be on the same huge page
(e.g. a 2MB page), so it is possible that there may be multiple items on
the same huge page in a repeater at the same time. In this case, L2 TLB
will release more than one repeater entry at a time (these pages are in
a same huge page). However, the req and resp of L2 TLB are one-to-one
correspondence, although one resp has returned, the resp of other reqs
are still inside L2 TLB, which means that the outstanding requests in L2
TLB are more than valid entries in repeater. In this case, there is no
guarantee that the L2 TLB will be able to accept as long as the repeater
is able to accept.

This problem becomes more pronounced when TLB compression (sector TLB)
is added and the repeater is reconfigured, which may result in more
situations that L2 TLB releasing more than one repeater entries at one
time. After refactoring the repeater, the three dtlb repeaters do not
check for duplicates, so L2 TLB resp may release entries from multiple
repeaters at the same time. Due to these reasons, in the high pressure
access situation especially after the hypervisor extension is
implemented, the MissQueue of L2 TLB may be filled while the repeater
cannot intercept (the repeater still has empty entries), which finally
resulting in a stuck.

This commit fixes this issue. The fix is straightforward, simply add a
counter at top level of L2 TLB to ensure that the number of outstanding
requests inside L2 TLB will not exceed the number of entries in
MissQueue. In future MMU refactoring, we should assign idx to L2 TLB
requests like freelist, so that we can solve the problem of stuckness,
and at the same time let MissQueue know the order of the requests, so as
to avoid the performance bug that the new requests are sent out first,
and the old ones are sent out later.

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fix(mnret): add the missing mnret output connection (#4194)

feat(XSNoCDiffTop): wrap XSNoCTop with Difftest Interface

To apply Difftest framework for CHI NoC, we wrapper lazy XSNoCTop
inside XSNoCDiffTop when difftest enabled, and expose necessary
soc/core/d

feat(XSNoCDiffTop): wrap XSNoCTop with Difftest Interface

To apply Difftest framework for CHI NoC, we wrapper lazy XSNoCTop
inside XSNoCDiffTop when difftest enabled, and expose necessary
soc/core/difftest IOs.

Currently we use two-step flow for CHI-NoC-XS as follow:
Step1. Generate single-core XSNoCDiffTop with JsonProfile,
which support generate another DifftestEndpoint seperately.
Step2. Generate n-core Difftest according to JsonProfile
Step3. Connect XS and Difftest manually or by some scripts.

As XSNoCDiffTop is only part of Difftest, we collect PerfCounters
for each DiffTop, need control signals passed from Outer module.
And to avoid potential connection problem, we add checker module
and CI test.

To maintain compatibility with previous IT/ST flow, we extend
XSNoCDiffTopConfig to enable difftest wrapper.

An example usage:
make verilog PLDM=1 PLDM_ARGS="--difftest-config H" CONFIG=XSNoCDiffTopConfig

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build(config): only allow to turn on or off CHIAsyncBridge (#4187)

feat(difftest): sync hgeip by difftest

fix(aia): add the missing AIA-related permission checks

Along the same lines, when hstatus.VGEIN is not the number of an implemented guest external
interrupt, attempts from M-mode or HS-mode to acce

fix(aia): add the missing AIA-related permission checks

Along the same lines, when hstatus.VGEIN is not the number of an implemented guest external
interrupt, attempts from M-mode or HS-mode to access CSR vstopei raise an illegal instruction
exception, and attempts from VS-mode to access stopei raise a virtual instruction exception.

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fix(Config): Use trim() instead of strip() for compatible with Java8 (#4184)

fix(Configs): set L3CacheParam or OpenLLCParam by EnableCHI (#4185)

fix(VFALU): fix bug of f16FirstFoldMaskUnorder when fold to 1/2 (#4181)

feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bo

feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bound.
Level-2: Fetch Latency Bound, Fetch Bandwidth Bound, Branch
Missprediction, machine clears, Core Bound, Memory Bound.
Leval-3: L1 Bound, L2 Bound, L3 Bound, Mem Bound, Store Bound.

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fix(L1PF, SMS): add pmp check (#4142)

**Checklist:**
1. no page/access fault
2. not uncache
3. no pmp access fault

**Changes:**
1. Add pmp response from PMPChecker
2. Wait until s3 phase to

fix(L1PF, SMS): add pmp check (#4142)

**Checklist:**
1. no page/access fault
2. not uncache
3. no pmp access fault

**Changes:**
1. Add pmp response from PMPChecker
2. Wait until s3 phase to process the response of TLB (got in s2) and
PMP(got in s3)

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fix(AXI4Memory): fix loss of `r` channel packet (#4176)

Co-authored-by: zhanglinjuan <[email protected]>

feat(custom, csr): add two custom CSRs mcorepwr and mflushpwr to control power (#4164)

Co-authored-by: Zhu Yu <[email protected]>

fix(PTWRepeater): use PriorityMux for not one-hot vector (#4174)

ptwResp_OldMatchVec is not a one-hot vector, so we should use
PriorityMux rather than OHToUInt.

timing(LoadUnit): optimization load unit writeback data generate logic (#4167)

optimization load unit writeback data generate logic
* merge multi source data at `s2`, select and expand data at `s3`

timing(LoadUnit): optimization load unit writeback data generate logic (#4167)

optimization load unit writeback data generate logic
* merge multi source data at `s2`, select and expand data at `s3`
* select data use one-hot instead of shifter

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feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 confi

feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 configurations:

- PmemRanges: physical memory ranges
- PMAConfigs
- CHIAsyncBridge: set depth to 0 to disable it
- L2CacheConfig
- L3CacheConfig
- DebugModuleBaseAddr

For better human-readability, this commit changes `WithNKBL2/3` to
`L2/3CacheConfig`, changing to case classes, and making the first
parameter only accept human-readable size configuration like `0.5 MB` or
`256kB`.

This commit also changes PMAConfigs and PmemRanges into List of case
classes.

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timing(LoadUnit): fpWen and pdest reg out (#4144)

when loadunit writeback
* **fpWen** uses register directly out
* **pdest** uses register directly out

feat(exception): divide the exceptions raised from CSR access into different sources (#4146)

Before this, we assumed that all possible exceptions during CSR read and
write operations should be handl

feat(exception): divide the exceptions raised from CSR access into different sources (#4146)

Before this, we assumed that all possible exceptions during CSR read and
write operations should be handled according to their priority.

Therefore, we ensured that all illegal instruction exceptions take
precedence over virtual instruction exceptions.

However, with the implementation of certain extensions like Smcsrind and
Smstateen, we encounter scenarios where virtual instruction exceptions
must take precedence over illegal instruction exceptions triggered.

For instance, when mstateen0.csrind is set to 1 and hstateen0.csrind is
0, a virtual instruction exception should be raised if VS mode attempts
to access sireg. However, if the vsiselect value is reserved in this
situation, an illegal instruction exception will be raised instead. If
these checks are treated as being at the same priority level, an illegal
instruction exception would ultimately be raised.

In reality, a virtual instruction exception should take precedence
because when the extension is disabled, we should not even evaluate the
value of vsiselect.

Therefore, we divided the sources of exceptions caused by CSR access
into several categories: M-level, S-level, privilege level,
virtualization level, and indirect access level.

Among them, M-level and S-level will only raise illegal instruction
exceptions, the privilege level will raise both illegal instruction and
virtual instruction exceptions, the virtualization level will raise
virtual instruction exceptions, and indirect access will raise both
illegal instruction and virtual instruction exceptions. Therefore, we
handle the exceptions from the previous levels in the same way, and only
check for exceptions caused by indirect access after ensuring that no
exceptions were raised earlier.

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fix(DM, SBA): add `TLWidthWidget` for sysbus

fix(CSR): fix xTIP update in sstcIRGen (#4157)

* The STIP signal is updated when:
* time.valid of clint
* stimecmp CSR is written
* menvcfg CSR is written

* The VSTIP signal is upda

fix(CSR): fix xTIP update in sstcIRGen (#4157)

* The STIP signal is updated when:
* time.valid of clint
* stimecmp CSR is written
* menvcfg CSR is written

* The VSTIP signal is updated when:
* time.valid of clint
* vstimecmp CSR is written
* htimedelta CSR is written
* menvcfg CSR is written
* henvcfg CSR is written

Co-authored-by: Xuan Hu <[email protected]>

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fix(device, DebugMoudle): do not use clock with Bool type (#4152)

* gsim can not handle such clocks