1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import device.MsiInfoBundle 24import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp} 25import freechips.rocketchip.tile.HasFPUParameters 26import system.HasSoCParameter 27import utils._ 28import utility._ 29import xiangshan.backend._ 30import xiangshan.backend.fu.PMPRespBundle 31import xiangshan.backend.trace.TraceCoreInterface 32import xiangshan.cache.mmu._ 33import xiangshan.frontend._ 34import scala.collection.mutable.ListBuffer 35import xiangshan.cache.mmu.TlbRequestIO 36 37abstract class XSModule(implicit val p: Parameters) extends Module 38 with HasXSParameter 39 with HasFPUParameters 40 41//remove this trait after impl module logic 42trait NeedImpl { 43 this: RawModule => 44 protected def IO[T <: Data](iodef: T): T = { 45 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 46 val io = chisel3.IO(iodef) 47 io <> DontCare 48 io 49 } 50} 51 52abstract class XSBundle(implicit val p: Parameters) extends Bundle 53 with HasXSParameter 54 55abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule 56 with HasXSParameter 57{ 58 override def shouldBeInlined: Boolean = false 59 // outer facing nodes 60 val frontend = LazyModule(new Frontend()) 61 val csrOut = BundleBridgeSource(Some(() => new DistributedCSRIO())) 62 val backend = LazyModule(new Backend(backendParams)) 63 64 val memBlock = LazyModule(new MemBlock) 65 66 memBlock.inner.frontendBridge.icache_node := frontend.inner.icache.clientNode 67 memBlock.inner.frontendBridge.instr_uncache_node := frontend.inner.instrUncache.clientNode 68 if (icacheParameters.cacheCtrlAddressOpt.nonEmpty) { 69 frontend.inner.icache.ctrlUnitOpt.get.node := memBlock.inner.frontendBridge.icachectrl_node 70 } 71} 72 73class XSCore()(implicit p: config.Parameters) extends XSCoreBase 74 with HasXSDts 75{ 76 lazy val module = new XSCoreImp(this) 77} 78 79class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) 80 with HasXSParameter 81 with HasSoCParameter { 82 val io = IO(new Bundle { 83 val hartId = Input(UInt(hartIdLen.W)) 84 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 85 val clintTime = Input(ValidIO(UInt(64.W))) 86 val reset_vector = Input(UInt(PAddrBits.W)) 87 val cpu_halt = Output(Bool()) 88 val cpu_critical_error = Output(Bool()) 89 val resetInFrontend = Output(Bool()) 90 val traceCoreInterface = new TraceCoreInterface 91 val l2_pf_enable = Output(Bool()) 92 val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent)) 93 val beu_errors = Output(new XSL1BusErrors()) 94 val l2_hint = Input(Valid(new L2ToL1Hint())) 95 val l2_tlb_req = Flipped(new TlbRequestIO(nRespDups = 2)) 96 val l2_pmp_resp = new PMPRespBundle 97 val l2PfqBusy = Input(Bool()) 98 val debugTopDown = new Bundle { 99 val robTrueCommit = Output(UInt(64.W)) 100 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 101 val l2MissMatch = Input(Bool()) 102 val l3MissMatch = Input(Bool()) 103 } 104 }) 105 106 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 107 108 val frontend = outer.frontend.module 109 val backend = outer.backend.module 110 val memBlock = outer.memBlock.module 111 112 frontend.io.hartId := memBlock.io.inner_hartId 113 frontend.io.reset_vector := memBlock.io.inner_reset_vector 114 frontend.io.softPrefetch <> memBlock.io.ifetchPrefetch 115 frontend.io.backend <> backend.io.frontend 116 frontend.io.sfence <> backend.io.frontendSfence 117 frontend.io.tlbCsr <> backend.io.frontendTlbCsr 118 frontend.io.csrCtrl <> backend.io.frontendCsrCtrl 119 frontend.io.fencei <> backend.io.fenceio.fencei 120 121 backend.io.fromTop := memBlock.io.mem_to_ooo.topToBackendBypass 122 123 require(backend.io.mem.stIn.length == memBlock.io.mem_to_ooo.stIn.length) 124 backend.io.mem.stIn.zip(memBlock.io.mem_to_ooo.stIn).foreach { case (sink, source) => 125 sink.valid := source.valid 126 sink.bits := 0.U.asTypeOf(sink.bits) 127 sink.bits.robIdx := source.bits.uop.robIdx 128 sink.bits.ssid := source.bits.uop.ssid 129 sink.bits.storeSetHit := source.bits.uop.storeSetHit 130 // The other signals have not been used 131 } 132 backend.io.mem.memoryViolation := memBlock.io.mem_to_ooo.memoryViolation 133 backend.io.mem.lsqEnqIO <> memBlock.io.ooo_to_mem.enqLsq 134 backend.io.mem.sqDeq := memBlock.io.mem_to_ooo.sqDeq 135 backend.io.mem.lqDeq := memBlock.io.mem_to_ooo.lqDeq 136 backend.io.mem.sqDeqPtr := memBlock.io.mem_to_ooo.sqDeqPtr 137 backend.io.mem.lqDeqPtr := memBlock.io.mem_to_ooo.lqDeqPtr 138 backend.io.mem.lqCancelCnt := memBlock.io.mem_to_ooo.lqCancelCnt 139 backend.io.mem.sqCancelCnt := memBlock.io.mem_to_ooo.sqCancelCnt 140 backend.io.mem.otherFastWakeup := memBlock.io.mem_to_ooo.otherFastWakeup 141 backend.io.mem.stIssuePtr := memBlock.io.mem_to_ooo.stIssuePtr 142 backend.io.mem.ldaIqFeedback := memBlock.io.mem_to_ooo.ldaIqFeedback 143 backend.io.mem.staIqFeedback := memBlock.io.mem_to_ooo.staIqFeedback 144 backend.io.mem.hyuIqFeedback := memBlock.io.mem_to_ooo.hyuIqFeedback 145 backend.io.mem.vstuIqFeedback := memBlock.io.mem_to_ooo.vstuIqFeedback 146 backend.io.mem.vlduIqFeedback := memBlock.io.mem_to_ooo.vlduIqFeedback 147 backend.io.mem.ldCancel := memBlock.io.mem_to_ooo.ldCancel 148 backend.io.mem.wakeup := memBlock.io.mem_to_ooo.wakeup 149 backend.io.mem.writebackLda <> memBlock.io.mem_to_ooo.writebackLda 150 backend.io.mem.writebackSta <> memBlock.io.mem_to_ooo.writebackSta 151 backend.io.mem.writebackHyuLda <> memBlock.io.mem_to_ooo.writebackHyuLda 152 backend.io.mem.writebackHyuSta <> memBlock.io.mem_to_ooo.writebackHyuSta 153 backend.io.mem.writebackStd <> memBlock.io.mem_to_ooo.writebackStd 154 backend.io.mem.writebackVldu <> memBlock.io.mem_to_ooo.writebackVldu 155 backend.io.mem.robLsqIO.mmio := memBlock.io.mem_to_ooo.lsqio.mmio 156 backend.io.mem.robLsqIO.uop := memBlock.io.mem_to_ooo.lsqio.uop 157 158 // memblock error exception writeback, 1 cycle after normal writeback 159 backend.io.mem.s3_delayed_load_error := memBlock.io.mem_to_ooo.s3_delayed_load_error 160 161 backend.io.mem.exceptionAddr.vaddr := memBlock.io.mem_to_ooo.lsqio.vaddr 162 backend.io.mem.exceptionAddr.gpaddr := memBlock.io.mem_to_ooo.lsqio.gpaddr 163 backend.io.mem.exceptionAddr.isForVSnonLeafPTE := memBlock.io.mem_to_ooo.lsqio.isForVSnonLeafPTE 164 backend.io.mem.debugLS := memBlock.io.debug_ls 165 backend.io.mem.lsTopdownInfo := memBlock.io.mem_to_ooo.lsTopdownInfo 166 backend.io.mem.lqCanAccept := memBlock.io.mem_to_ooo.lsqio.lqCanAccept 167 backend.io.mem.sqCanAccept := memBlock.io.mem_to_ooo.lsqio.sqCanAccept 168 backend.io.fenceio.sbuffer.sbIsEmpty := memBlock.io.mem_to_ooo.sbIsEmpty 169 170 backend.io.perf.frontendInfo := frontend.io.frontendInfo 171 backend.io.perf.memInfo := memBlock.io.memInfo 172 backend.io.perf.perfEventsFrontend := frontend.io_perf 173 backend.io.perf.perfEventsLsu := memBlock.io_perf 174 backend.io.perf.perfEventsHc := memBlock.io.inner_hc_perfEvents 175 backend.io.perf.perfEventsBackend := DontCare 176 backend.io.perf.retiredInstr := DontCare 177 backend.io.perf.ctrlInfo := DontCare 178 179 backend.io.mem.storeDebugInfo <> memBlock.io.mem_to_ooo.storeDebugInfo 180 181 // top -> memBlock 182 memBlock.io.fromTopToBackend.clintTime := io.clintTime 183 memBlock.io.fromTopToBackend.msiInfo := io.msiInfo 184 memBlock.io.hartId := io.hartId 185 memBlock.io.outer_reset_vector := io.reset_vector 186 memBlock.io.outer_hc_perfEvents := io.perfEvents 187 // frontend -> memBlock 188 memBlock.io.inner_beu_errors_icache <> frontend.io.error.bits.toL1BusErrorUnitInfo(frontend.io.error.valid) 189 memBlock.io.inner_l2_pf_enable := backend.io.csrCustomCtrl.l2_pf_enable 190 memBlock.io.ooo_to_mem.backendToTopBypass := backend.io.toTop 191 memBlock.io.ooo_to_mem.issueLda <> backend.io.mem.issueLda 192 memBlock.io.ooo_to_mem.issueSta <> backend.io.mem.issueSta 193 memBlock.io.ooo_to_mem.issueStd <> backend.io.mem.issueStd 194 memBlock.io.ooo_to_mem.issueHya <> backend.io.mem.issueHylda 195 backend.io.mem.issueHysta.foreach(_.ready := false.B) // this fake port should not be used 196 memBlock.io.ooo_to_mem.issueVldu <> backend.io.mem.issueVldu 197 198 // By default, instructions do not have exceptions when they enter the function units. 199 memBlock.io.ooo_to_mem.issueUops.map(_.bits.uop.clearExceptions()) 200 memBlock.io.ooo_to_mem.storePc := backend.io.mem.storePcRead 201 memBlock.io.ooo_to_mem.hybridPc := backend.io.mem.hyuPcRead 202 memBlock.io.ooo_to_mem.flushSb := backend.io.fenceio.sbuffer.flushSb 203 memBlock.io.ooo_to_mem.loadFastMatch := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastMatch) 204 memBlock.io.ooo_to_mem.loadFastImm := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastImm) 205 memBlock.io.ooo_to_mem.loadFastFuOpType := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastFuOpType) 206 207 memBlock.io.ooo_to_mem.sfence <> backend.io.mem.sfence 208 209 memBlock.io.redirect := backend.io.mem.redirect 210 memBlock.io.ooo_to_mem.csrCtrl := backend.io.mem.csrCtrl 211 memBlock.io.ooo_to_mem.tlbCsr := backend.io.mem.tlbCsr 212 memBlock.io.ooo_to_mem.lsqio.lcommit := backend.io.mem.robLsqIO.lcommit 213 memBlock.io.ooo_to_mem.lsqio.scommit := backend.io.mem.robLsqIO.scommit 214 memBlock.io.ooo_to_mem.lsqio.pendingMMIOld := backend.io.mem.robLsqIO.pendingMMIOld 215 memBlock.io.ooo_to_mem.lsqio.pendingld := backend.io.mem.robLsqIO.pendingld 216 memBlock.io.ooo_to_mem.lsqio.pendingst := backend.io.mem.robLsqIO.pendingst 217 memBlock.io.ooo_to_mem.lsqio.pendingVst := backend.io.mem.robLsqIO.pendingVst 218 memBlock.io.ooo_to_mem.lsqio.commit := backend.io.mem.robLsqIO.commit 219 memBlock.io.ooo_to_mem.lsqio.pendingPtr := backend.io.mem.robLsqIO.pendingPtr 220 memBlock.io.ooo_to_mem.lsqio.pendingPtrNext := backend.io.mem.robLsqIO.pendingPtrNext 221 memBlock.io.ooo_to_mem.isStoreException := backend.io.mem.isStoreException 222 memBlock.io.ooo_to_mem.isVlsException := backend.io.mem.isVlsException 223 224 memBlock.io.fetch_to_mem.itlb <> frontend.io.ptw 225 memBlock.io.l2_hint.valid := io.l2_hint.valid 226 memBlock.io.l2_hint.bits.sourceId := io.l2_hint.bits.sourceId 227 memBlock.io.l2_tlb_req <> io.l2_tlb_req 228 memBlock.io.l2_pmp_resp <> io.l2_pmp_resp 229 memBlock.io.l2_hint.bits.isKeyword := io.l2_hint.bits.isKeyword 230 memBlock.io.l2PfqBusy := io.l2PfqBusy 231 232 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 233 234 // top-down info 235 memBlock.io.debugTopDown.robHeadVaddr := backend.io.debugTopDown.fromRob.robHeadVaddr 236 frontend.io.debugTopDown.robHeadVaddr := backend.io.debugTopDown.fromRob.robHeadVaddr 237 io.debugTopDown.robHeadPaddr := backend.io.debugTopDown.fromRob.robHeadPaddr 238 io.debugTopDown.robTrueCommit := backend.io.debugRolling.robTrueCommit 239 backend.io.debugTopDown.fromCore.l2MissMatch := io.debugTopDown.l2MissMatch 240 backend.io.debugTopDown.fromCore.l3MissMatch := io.debugTopDown.l3MissMatch 241 backend.io.debugTopDown.fromCore.fromMem := memBlock.io.debugTopDown.toCore 242 memBlock.io.debugRolling := backend.io.debugRolling 243 244 io.cpu_halt := memBlock.io.outer_cpu_halt 245 io.cpu_critical_error := memBlock.io.outer_cpu_critical_error 246 io.beu_errors.icache <> memBlock.io.outer_beu_errors_icache 247 io.beu_errors.dcache <> memBlock.io.error.bits.toL1BusErrorUnitInfo(memBlock.io.error.valid) 248 io.beu_errors.l2 <> DontCare 249 io.l2_pf_enable := memBlock.io.outer_l2_pf_enable 250 251 memBlock.io.resetInFrontendBypass.fromFrontend := frontend.io.resetInFrontend 252 io.resetInFrontend := memBlock.io.resetInFrontendBypass.toL2Top 253 memBlock.io.traceCoreInterfaceBypass.fromBackend <> backend.io.traceCoreInterface 254 io.traceCoreInterface <> memBlock.io.traceCoreInterfaceBypass.toL2Top 255 256 257 if (debugOpts.ResetGen) { 258 backend.reset := memBlock.io.reset_backend 259 frontend.reset := backend.io.frontendReset 260 } 261} 262