chore: fix several deprecation warning (#4352)

feat(AIA): integrate ChiselAIA (#4378)

feat(Difftest): add multi-core vector load check (#4361)

Currently, we implement the multi core vector load check in difftest.
We modified difftest and NEMU and added related content in XiangShan.

config: add fpga diff top on tilelink for diff_top (#4370)

In order to be compatible with st's environment, the fpga difftest
project in tilelink is generated in the same way as noc top, which leads

config: add fpga diff top on tilelink for diff_top (#4370)

In order to be compatible with st's environment, the fpga difftest
project in tilelink is generated in the same way as noc top, which leads
tilelink top and difftest signals to difftop together.

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fix(Trigger): fix comparison between consecutive pc and tdada2 (#4346)

fix(CSR): add VTYPE to in-order read CSRs (#4354)

Since CSR VTYPE is not renamed (VL is renamed), the instruction CSRR
with VTYPE cannot be executed out-of-order.

fix(LSU): misaligned violation detection stuck (#4369)

Since a load instruction that cross 16Byte needs to be split and
accessed twice, it needs to enter the `RAR Queue` twice, but occupies
only one

fix(LSU): misaligned violation detection stuck (#4369)

Since a load instruction that cross 16Byte needs to be split and
accessed twice, it needs to enter the `RAR Queue` twice, but occupies
only one `virtual load queue`, so in the extreme case it may happen that
36 load instructions that span 16Byte fill all 72 `RAR queues`.

---

There is some problem with our previous handling; if the oldest load
instruction spanning 16Byte enters the `replayqueue` and at the same
time there exists an instruction in the `loadmisalignbuffer` that can't
finish executing because the `RAR Queue` is full, then the oldest load
instruction is never cannot be issued because the `loadmisalignbuffer`
has instructions in it all the time.

---

Therefore, we use a more violent scheme to do this.
When the RAR is full, we let the misaligned load generate a rollback,
and the next load instruction that the loadmisalignbuffer can receive
must be the oldest (if it is misaligned).

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fix(vlbusytable): fix vlbusytable update (#4364)

chore(fu): delete redundant code in VCVT (#4328)

fix(LoadUnit): enable EnableAccurateLoadError (#4363)

fix(LoadUnit): exclude prefetch requests (#4367)

* In order to ensure timing, the RAR enqueue conditions need to be
compromised, worst source of timing from `pmp` and `missQueue`.

* if `LoadQueueRA

fix(LoadUnit): exclude prefetch requests (#4367)

* In order to ensure timing, the RAR enqueue conditions need to be
compromised, worst source of timing from `pmp` and `missQueue`.

* if `LoadQueueRARSize` == `VirtualLoadQueueSize`, just need to exclude
prefetching.

* if `LoadQueueRARSize` < `VirtualLoadQueueSize`, need to consider the
situation of `s2_can_query`

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fix(MainPipe): fix `s3_l2_error` and `s3_error` enable signal (#4345)

* `s2_fire` and `s2_can_to_s3` are different
* `io.error.valid` uses `s2_fire`, but `s3_l2_error` uses
`s2_can_to_s3`, causing

fix(MainPipe): fix `s3_l2_error` and `s3_error` enable signal (#4345)

* `s2_fire` and `s2_can_to_s3` are different
* `io.error.valid` uses `s2_fire`, but `s3_l2_error` uses
`s2_can_to_s3`, causing `io.error.valid` to be updated, but
`s3_l2_error` not to be updated.

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fix(LoadUnit): misalign wakeup should not set s0 valid (#4359)

`s0_src_valid_vec` is not `s0_src_select_vec`, and bit corresponding to
`s0_src_valid_vec` is valid when any of the inputs `valid`. The

fix(LoadUnit): misalign wakeup should not set s0 valid (#4359)

`s0_src_valid_vec` is not `s0_src_select_vec`, and bit corresponding to
`s0_src_valid_vec` is valid when any of the inputs `valid`. Therefore,
`misalign wakeup` needs to globally control `s0_valid`.

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build: can manually disable dfx by `DFX=0` (#4353)

feat(Top): remain dfx io for `XSTile` under `Top.scala` (#4351)

fix(MMU): incorrect generation of Exception vaddr (#4349)

The preivous GenExceptionVa function makes some mistakes in selecting
the exception vaddr when exception. The check for S-stage, VS-stage an

fix(MMU): incorrect generation of Exception vaddr (#4349)

The preivous GenExceptionVa function makes some mistakes in selecting
the exception vaddr when exception. The check for S-stage, VS-stage and
G-stage are mixed together, which causes the one-hot signal to be wrong.

This patch rewrites the relative logic and fixes the bug.

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fix(DCache): use `ParallelMux` instead of `Mux1H` (#4340)

* When there are multiple errors，`Mux1H` is equivalent to using `|`, for
example

* error 0, valid = 1, addr0 = 0x1000
* error 1, va

fix(DCache): use `ParallelMux` instead of `Mux1H` (#4340)

* When there are multiple errors，`Mux1H` is equivalent to using `|`, for
example

* error 0, valid = 1, addr0 = 0x1000
* error 1, valid = 1, addr1 = 0x0ffff
* the result is `io.error.valid == 1`, but `io.error.bits.addr == (addr0
| addr1)`, cause `Mux1H` will generate circuit like this:
```
addr = (valid0 ? addr0 : 'h0) |
(valid1 ? addr1 : 'h0)
```
* This problem can be avoided by using `ParallelMux`

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feat(BEU): beu will trigger `NMI_31` non-maskable interrupt (#4335)

* use `NMI_31` is ok

fix(DCache): fix wrong condition for blocking lr (#4337)

Following lr should be blocked when previous lr's resv_set is still
valid, which means `lrsc_count > 0`.

In previous PR #3017 and #4117, `lr

fix(DCache): fix wrong condition for blocking lr (#4337)

Following lr should be blocked when previous lr's resv_set is still
valid, which means `lrsc_count > 0`.

In previous PR #3017 and #4117, `lrsc_count > 8` is used as block
condition, and stop update `lrsc_count` when it reaches 8, fix it now.

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fix(LoadUnit): misalign load wakeup not enter loadunit (#4333)

feat(RAS): change the stall mechanism upon return stack overflow to dynamically disable the return stack. (#4317)

1. Predictor pipeline stalls exhibit poor fault tolerance.
2. Speculative queue over

feat(RAS): change the stall mechanism upon return stack overflow to dynamically disable the return stack. (#4317)

1. Predictor pipeline stalls exhibit poor fault tolerance.
2. Speculative queue overflow (requiring 32 uncommitted call/return
instructions) is an extreme scenario where disabling return stack
prediction incurs negligible performance impact.
3. Queue overflow often indicates recursion. In such cases, using
top-of-stack data (static return addresses) may outperform IT-TAGE
predictions despite disabled return stack.

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fix(PFEvent): use `CSRModule` for distribute_csr in PFEvent (#4321)

timing(LoadQueueRAR, LoadUnit): adjust rar/raw query logic (#4297)

* Because of `LoadQueueRARSize == VirtualLoadQueueSize`, so no need to
add additional logic for rar enq
* When no need fast replay,

timing(LoadQueueRAR, LoadUnit): adjust rar/raw query logic (#4297)

* Because of `LoadQueueRARSize == VirtualLoadQueueSize`, so no need to
add additional logic for rar enq
* When no need fast replay, loadunit allocate raw entry

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fix(LDU): nc is also not mis-aligned (#4326)

fix(L2top): Shouldn't subtract dm from mmio_port when SeperateDMBus disable (#4324)