1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: 9# http://license.coscl.org.cn/MulanPSL2 10# 11# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14# 15# See the Mulan PSL v2 for more details. 16#*************************************************************************************** 17 18BUILD_DIR = ./build 19RTL_DIR = $(BUILD_DIR)/rtl 20 21TOP = $(XSTOP_PREFIX)XSTop 22SIM_TOP = SimTop 23 24FPGATOP = top.TopMain 25SIMTOP = top.SimTop 26 27RTL_SUFFIX ?= sv 28TOP_V = $(RTL_DIR)/$(TOP).$(RTL_SUFFIX) 29SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX) 30 31SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 32TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 33 34MEM_GEN = ./scripts/vlsi_mem_gen 35MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 36 37CONFIG ?= DefaultConfig 38NUM_CORES ?= 1 39ISSUE ?= E.b 40CHISEL_TARGET ?= systemverilog 41 42SUPPORT_CHI_ISSUE = B C E.b 43ifeq ($(findstring $(ISSUE), $(SUPPORT_CHI_ISSUE)),) 44$(error "Unsupported CHI issue: $(ISSUE)") 45endif 46 47ifneq ($(shell echo "$(MAKECMDGOALS)" | grep ' '),) 48$(error At most one target can be specified) 49endif 50 51ifeq ($(MAKECMDGOALS),) 52GOALS = verilog 53else 54GOALS = $(MAKECMDGOALS) 55endif 56 57# JVM memory configurations 58JVM_XMX ?= 40G 59JVM_XSS ?= 256m 60 61# mill arguments for build.sc 62MILL_BUILD_ARGS = -Djvm-xmx=$(JVM_XMX) -Djvm-xss=$(JVM_XSS) 63 64# common chisel args 65FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf" 66SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf" 67MFC_ARGS = --dump-fir --target $(CHISEL_TARGET) --split-verilog \ 68 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" 69 70# prefix of XSTop or XSNoCTop 71ifneq ($(XSTOP_PREFIX),) 72COMMON_EXTRA_ARGS += --xstop-prefix $(XSTOP_PREFIX) 73endif 74 75# IMSIC use TileLink rather than AXI4Lite 76ifeq ($(IMSIC_USE_TL),1) 77COMMON_EXTRA_ARGS += --imsic-use-tl 78endif 79 80# enable or disable dfx manually 81ifeq ($(DFX),1) 82COMMON_EXTRA_ARGS += --dfx true 83else 84ifeq ($(DFX),0) 85COMMON_EXTRA_ARGS += --dfx false 86endif 87endif 88 89# L2 cache size in KB 90ifneq ($(L2_CACHE_SIZE),) 91COMMON_EXTRA_ARGS += --l2-cache-size $(L2_CACHE_SIZE) 92endif 93 94# L3 cache size in KB 95ifneq ($(L3_CACHE_SIZE),) 96COMMON_EXTRA_ARGS += --l3-cache-size $(L3_CACHE_SIZE) 97endif 98 99# seperate bus for DebugModule 100ifeq ($(SEPERATE_DM_BUS),1) 101COMMON_EXTRA_ARGS += --seperate-dm-bus 102endif 103 104# configuration from yaml file 105ifneq ($(YAML_CONFIG),) 106COMMON_EXTRA_ARGS += --yaml-config $(YAML_CONFIG) 107endif 108 109# public args sumup 110RELEASE_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 111DEBUG_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 112override PLDM_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 113 114# co-simulation with DRAMsim3 115ifeq ($(WITH_DRAMSIM3),1) 116ifndef DRAMSIM3_HOME 117$(error DRAMSIM3_HOME is not set) 118endif 119override SIM_ARGS += --with-dramsim3 120endif 121 122# run emu with chisel-db 123ifeq ($(WITH_CHISELDB),1) 124override SIM_ARGS += --with-chiseldb 125endif 126 127# run emu with chisel-db 128ifeq ($(WITH_ROLLINGDB),1) 129override SIM_ARGS += --with-rollingdb 130endif 131 132# enable ResetGen 133ifeq ($(WITH_RESETGEN),1) 134override SIM_ARGS += --reset-gen 135endif 136 137# run with disable all perf 138ifeq ($(DISABLE_PERF),1) 139override SIM_ARGS += --disable-perf 140endif 141 142# run with disable all db 143ifeq ($(DISABLE_ALWAYSDB),1) 144override SIM_ARGS += --disable-alwaysdb 145endif 146 147# dynamic switch CONSTANTIN 148ifeq ($(WITH_CONSTANTIN),1) 149override SIM_ARGS += --with-constantin 150endif 151 152# emu for the release version 153RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen --firtool-opt --ignore-read-enable-mem 154DEBUG_ARGS += --enable-difftest 155override PLDM_ARGS += --enable-difftest 156ifeq ($(RELEASE),1) 157override SIM_ARGS += $(RELEASE_ARGS) 158else ifeq ($(PLDM),1) 159override SIM_ARGS += $(PLDM_ARGS) 160else 161override SIM_ARGS += $(DEBUG_ARGS) 162endif 163 164# use RELEASE_ARGS for TopMain by default 165ifeq ($(PLDM), 1) 166TOPMAIN_ARGS += $(PLDM_ARGS) 167else 168TOPMAIN_ARGS += $(RELEASE_ARGS) 169endif 170 171TIMELOG = $(BUILD_DIR)/time.log 172TIME_CMD = time -avp -o $(TIMELOG) 173 174ifeq ($(PLDM),1) 175SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 176SED_ENDIF = `endif // not def SYNTHESIS 177endif 178 179.DEFAULT_GOAL = verilog 180 181help: 182 mill -i xiangshan.runMain $(FPGATOP) --help 183 184version: 185 mill -i xiangshan.runMain $(FPGATOP) --version 186 187jar: 188 mill -i xiangshan.assembly 189 190test-jar: 191 mill -i xiangshan.test.assembly 192 193comp: 194 mill -i xiangshan.compile 195 mill -i xiangshan.test.compile 196 197$(TOP_V): $(SCALA_FILE) 198 mkdir -p $(@D) 199 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.runMain $(FPGATOP) \ 200 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS) \ 201 --num-cores $(NUM_CORES) $(TOPMAIN_ARGS) 202ifeq ($(CHISEL_TARGET),systemverilog) 203 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 204 @git log -n 1 >> .__head__ 205 @git diff >> .__diff__ 206 @sed -i 's/^/\/\// ' .__head__ 207 @sed -i 's/^/\/\//' .__diff__ 208 @cat .__head__ .__diff__ $@ > .__out__ 209 @mv .__out__ $@ 210 @rm .__head__ .__diff__ 211endif 212 213verilog: $(TOP_V) 214 215$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 216 mkdir -p $(@D) 217 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG) 218 @date -R | tee -a $(TIMELOG) 219 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.test.runMain $(SIMTOP) \ 220 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(SIM_MEM_ARGS) \ 221 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 222ifeq ($(CHISEL_TARGET),systemverilog) 223 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 224 @git log -n 1 >> .__head__ 225 @git diff >> .__diff__ 226 @sed -i 's/^/\/\// ' .__head__ 227 @sed -i 's/^/\/\//' .__diff__ 228 @cat .__head__ .__diff__ $@ > .__out__ 229 @mv .__out__ $@ 230 @rm .__head__ .__diff__ 231ifeq ($(PLDM),1) 232 sed -i -e 's/$$fatal/$$finish/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 233 sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(RTL_DIR)/*.$(RTL_SUFFIX) 234else 235ifeq ($(ENABLE_XPROP),1) 236 sed -i -e "s/\$$fatal/assert(1\'b0)/g" $(RTL_DIR)/*.$(RTL_SUFFIX) 237else 238 sed -i -e 's/$$fatal/xs_assert_v2(`__FILE__, `__LINE__)/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 239endif 240endif 241 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(RTL_DIR)/*.$(RTL_SUFFIX) 242endif 243 244sim-verilog: $(SIM_TOP_V) 245 246clean: 247 $(MAKE) -C ./difftest clean 248 rm -rf $(BUILD_DIR) 249 250init: 251 git submodule update --init 252 cd rocket-chip && git submodule update --init cde hardfloat 253 cd openLLC && git submodule update --init openNCB 254 255bump: 256 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 257 258bsp: 259 mill -i mill.bsp.BSP/install 260 261idea: 262 mill -i mill.idea.GenIdea/idea 263 264check-format: 265 mill xiangshan.checkFormat 266 267reformat: 268 mill xiangshan.reformat 269 270# verilator simulation 271emu: sim-verilog 272 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 273 274emu-run: emu 275 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 276 277# vcs simulation 278simv: sim-verilog 279 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 280 281simv-run: 282 $(MAKE) -C ./difftest simv-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 283 284# palladium simulation 285pldm-build: sim-verilog 286 $(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 287 288pldm-run: 289 $(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 290 291pldm-debug: 292 $(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 293 294include Makefile.test 295 296include src/main/scala/device/standalone/standalone_device.mk 297 298.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 299