Merge branch 'master' into vaddr-fwd

icache: add license

config: remove MinimalSimConfigForFetch

bundle: code clean ups

bundle, xscore: code clean ups

Merge remote-tracking branch 'origin/master' into decoupled-frontend

Merge remote-tracking branch 'origin/master' into vaddr-fwd

Revert "mem: add load to load addr fastpath framework"

This reverts commit e3f759ae573d6f4fabbfe9e4dcf7987b1d32d06d.

fudian: The new floating-point lib to replace hardfloat (#975)

* Add submodule 'fudian'

* IntToFP: use fudian

* FMA: use fudian.CMA

* FPToInt: remove recode format

Merge branch 'master' into dcp-merge-master

backend, rename: support move elimination (#920)

* Bundle, Rename: Add some comments
FreeList, RenameTable: Comment out unused variables

* refcnt: Implement AdderTree for reference counter

*

backend, rename: support move elimination (#920)

* Bundle, Rename: Add some comments
FreeList, RenameTable: Comment out unused variables

* refcnt: Implement AdderTree for reference counter

* build.sc: add testOne method for unit test

* AdderTest: add testbench for Adder (passed)

* AdderTree: Add testbench for AdderTree (passed)

* ReferenceCounter: implement a 2-bit counter

* Rename: remove redundant code

* Rename: prepared for move elimination [WIP]

* Roq: add eliminated move bit in roq entry;
label elim move inst as writebacked
AlternativeFreeList: new impl for int free list
Rename: change io of free list
Dispatch1: (todo) not send move to intDq
Bundle: add eliminatedMove bit in roqCommitInfo, uop and debugio
ReferenceCounter: add debug print msg

* Dispatch1: [BUG FIX] not send move inst to IntDq

* DecodeUnit: [BUG FIX] differentiate li from mv

* Bug fix:
1. Dispatch1: should not label pdest of move as busy in busy table
2. Rename: use psrc0 to index bit vec isMax
3. AlternativeFreeList: fix maxVec calculation logic and ref counter
increment logic
Besides, more debug info and assertions were added.

* AlternativeFreeList Bug Fix:
1. add redirect input - shouldn't allocate reg when redirect is
valid
2. handle duplicate preg in roqCommits in int free list

* AlternativeFreeList: Fix value assignment race condition

* Rename: Fix value assignment race condition too

* RenameTable: refactor spec/arch table write process

* Roq: Fix debug_exuData of move(addi) instruction
(it was trash data before because move needn't enter exu)

* Rename: change intFreeList's redirect process
(by setting headPtr back) and flush process

* ME: microbench & coremark & linux-hello passed
1. DecodeUnit: treat `mv x,x` inst as non-move
2. AlternativeFreeList: handle duplicate walk req correctly
3. Roq: fix debug_exuData bug (make sure writeback that updates
debug_exuData happens before ME instruction in program order)

* AlternativeFreeList: License added
build.sc: remove unused config
Others: comments added

* package rename: remove unused modules

* Roq: Replace debug_prf with a cleaner fix method

* Disp1/AltFL/Rename: del unnecessary white spaces

* build.sc: change stack size
AlternativeFreeList: turn off assertions

* build.sc: change stack size for test

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frontend: enable fast enq to ftq, and move tage to stage2

[WIP] BPU: Modify BPU and Ftq interfaces

fix bug calc backendRedirectCfi.shift

ftq: update interface

[WIP] BPU: Add lastStage function in

frontend: enable fast enq to ftq, and move tage to stage2

[WIP] BPU: Modify BPU and Ftq interfaces

fix bug calc backendRedirectCfi.shift

ftq: update interface

[WIP] BPU: Add lastStage function in BranchPredictionResp

[WIP] BPU: Move Tage to s2

[WIP] BPU: Fix some bugs

ftq: add fast enq logic

[WIP] BPU: Move RAS to s2

bpu: s2 and s3 valid should consider corresponding flush signal

[WIP] BPU: When s1_valid and s2_valid all false,

s3 target need compare with s0_pc_reg, s3_predicted_ghit as well

[WIP] BPU: Move resp.s3 assignment from Tage to RAS

[WIP] BPU: Fix bug that Tage send meta in s2

[WIP] BPU: Add brOffset and jmpOffset in ubtb

tage-sc: fix typos

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mem: add load to load addr fastpath framework

core: add basic debug mode features (#918)

Basic features of debug mode are implemented.

* Rewrite CSR for debug mode
* Peripheral work for implementing debug module
* Added single step support

core: add basic debug mode features (#918)

Basic features of debug mode are implemented.

* Rewrite CSR for debug mode
* Peripheral work for implementing debug module
* Added single step support
* Use difftest with JTAG support

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Merge branch 'decoupled-frontend-ifu' into decoupled-frontend

ctrlblock: remove redirect_cfiUpdate port, and use stage3Redirect

rob: support replay inst from rob

Merge branch 'master' into merge-master

Merge remote-tracking branch 'origin/decoupled-bpu' into decoupled-frontend

bpu: support parameterizetion of path history length

bpu: add support for path hist

BPU: Modify the branch history update logic, update according to each br instruction

bpu: Add Tage

Add Tage into Composer
Add global history manage logic in BPU
Modify CfiUpdate interface: sawNotTakenBranch -> br_hit

Update difftest to use NEMU master branch (#902)

misc: implement difftest as a submodule

misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

[WIP] finish ftq logic and fix syntax errors

* Now can pass compiling.

[WIP] comment out-of-date code in frontend

[WIP] move NewFtq to xiangshan.frontend and rename class to Ftq

Ibuffer: update s

[WIP] finish ftq logic and fix syntax errors

* Now can pass compiling.

[WIP] comment out-of-date code in frontend

[WIP] move NewFtq to xiangshan.frontend and rename class to Ftq

Ibuffer: update sigal names for new IFU

[WIP] remove redundant NewFrontend

[WIP] set entry_fetch_status to f_sent once send req to buf

Fix syntax error in IFU

Fix syntax error in IFU/ICache/Ibuffer

[WIP] indent fix in ftq

BPU: Move GlobalHistory define from IFU.scala to BPU.scala

[WIP] fix some compilation errors

BPU: Remove HasIFUConst
and move some bundles from BPU.scala to frontendBundle.scala

[WIP] fix some compilation errors

[WIP] rename ftq-bpu ios

[WIP] recover some const definitions

[WIP] fix some compilation errors

[WIP]connect some IOs in frontend

BPU: fix syntax error

[WIP] fix compilation errors in predecode

BPU: fix RAS syntax error

[WIP] add some simulation perf counters back

BPU: Remove numBr redefine in ubtb and bim

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core: move ftq to frontend

[WIP]Frontend: Done Elaborating