Fix vcs simulation support, support manually set ram_size (#1551)

* difftest: disable runahead to make vcs happy

* difftest: bump huancun to make vcs happy

* difftest: bump difftest and ready-

Fix vcs simulation support, support manually set ram_size (#1551)

* difftest: disable runahead to make vcs happy

* difftest: bump huancun to make vcs happy

* difftest: bump difftest and ready-to-run

* difftest support ramsize and paddr base config
* 8GB/16GB nemu so are provided by ready-to-run

* ci: update nightly ci, manually set ram_size

* difftest: bump huancun to make vcs happy

* difftest,nemu: support run-time assign mem size

* ci: polish nightly ci script

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ci: add nightly regression with Spike (#1544)

scripts: use physical cores only

scripts: support diff with spike

ci: add smp linux (#1465)

mem: fix ldld vio check implementation (#1456)

* mem: fix ldld vio mask gen logic

* mem: fix lq released flag update logic

Make sure that every load before a probe has correct released flag

mem: fix ldld vio check implementation (#1456)

* mem: fix ldld vio mask gen logic

* mem: fix lq released flag update logic

Make sure that every load before a probe has correct released flag

See the PR of this commit for illustration

* mem: fix ld-ld violation check logic

* ci: clean up workspace before do real test

* mem: reduce lq released flag update delay for 1 cycle

* chore: bump difftest to run no-smp diff

* ci: add mc test

* mem: fix lq released flag update logic

* chore: set difftest firstCommit_limit to 10000

* ci: use dual-nemu-so for mc test

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ci: moved to BOSC servers (#1437)

scripts,xs: ignore get_cores when numa is not set (#1397)

ci: add cacheop test (without difftest) (#1370)

* difftest: bump difftest to support --no-diff test

* ci: add cacheoptest test (--no-diff)

csr: add write mask to satp.ppn & xstatus.xs (#1323)

* csr.satp: add r/w mask of ppn part

* ci: add unit test, satp should concern PADDRBITS

* csr.xstatus: XS field is ready-only

* bump rea

csr: add write mask to satp.ppn & xstatus.xs (#1323)

* csr.satp: add r/w mask of ppn part

* ci: add unit test, satp should concern PADDRBITS

* csr.xstatus: XS field is ready-only

* bump ready-to-run

* bump ready-to-run, update nemu so

* fix typo

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Updated to priv 1.12 (#1301)

* csr: clear mstatus.mprv when mstatus.mpp != ModeM at xret

* csr: add mconfigptr, but hardwire to 0 now

* csr: add *BE to mstatusStruct which are hardwired to 0

Updated to priv 1.12 (#1301)

* csr: clear mstatus.mprv when mstatus.mpp != ModeM at xret

* csr: add mconfigptr, but hardwire to 0 now

* csr: add *BE to mstatusStruct which are hardwired to 0

* csr: fix bug of xret clear mprv

* ci: add unit test, xret clear mstatus.mprv when xpp is not M

* bump ready-to-run

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scripts: add dynamic numactl for emu run (#1304)

script: fix visualization script of tl-logger (#1229)

top: enable fpga option for simulation emu (#1213)

* disable log as default
* code clean up

Svinval (#1055)

* Svinval: implement Svinval
* add three new instructions(SINVAL_VMA SFENCE_W_INVAL SFENCE_INVAL_IR)
* TODO : test

* Prevent illegal software code by adding an assert
* make sure th

Svinval (#1055)

* Svinval: implement Svinval
* add three new instructions(SINVAL_VMA SFENCE_W_INVAL SFENCE_INVAL_IR)
* TODO : test

* Prevent illegal software code by adding an assert
* make sure the software runs as follow:
begin instruction of svinval extension
svinval xxxx
svinval xxxx
...
end instruction of svinval extension

* Svinval: add an CSR to control it and some annotations

* Roq: fix assert bug of Svinval

* Svinval: fix svinval.vma's rs2 type
* make it reg instead of imm

* Svinval: change assert logic and fix bug
* fix the condition judging Svinval.vma instruction
* using doingSvinval in assert

* ci: add rv64mi-p-svinval to ci

* fix typo

* fix bug that lost ','

* when svinval disable, raise illegal instr excep

* CSR: mv svinval ctl to srnctl(1)

* rob: when excep, do not set dosvinval

* decode: when disable svinval, do not set flushpipe

* bump ready-to-run

Co-authored-by: ZhangZifei <[email protected]>

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bump ready-to-run (#1173)

misc: do bug fix (#1157)

* bump difftest & huancun

asid: add asid, mainly work when hit check, not in sfence.vma (#1090)

add mmu's asid support.
1. put asid inside sram (if the entry is sram), or it will take too many sources.
2. when sfence, just

asid: add asid, mainly work when hit check, not in sfence.vma (#1090)

add mmu's asid support.
1. put asid inside sram (if the entry is sram), or it will take too many sources.
2. when sfence, just flush it all, don't care asid.
3. when hit check, check asid.
4. when asid changed, flush all the inflight ptw req for safety
5. simple asid unit test:
asid 1 write, asid 2 read and check, asid 2 write, asid 1 read and check. same va, different pa

* ASID: make satp's asid bits configurable to RW
* use AsidLength to control it

* ASID: implement asid refilling and hit checking
* TODO: sfence flush with asid

* ASID: implement sfence with asid
* TODO: extract asid from SRAMTemplate

* ASID: extract asid from SRAMTemplate
* all is down
* TODO: test

* fix write to asid

* Sfence: support rs2 of sfence and fix Fence Unit
* rs2 of Sfence should be Reg and pass it to Fence Unit
* judge the value of reg instead of the index in Fence Unit

* mmu: re-write asid

now, asid is stored inside sram, so sfence just flush it
it's a complex job to handle the problem that asid is changed but
no sfence.vma is executed. when asid is changed, all the inflight
mmu reqs are flushed but entries in storage is not influenced.
so the inflight reqs do not need to record asid, just use satp.asid

* tlb: fix bug of refill mask

* ci: add asid unit test

Co-authored-by: ZhangZifei <[email protected]>

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l2tlb: add next-line prefetcher (#1108)

预取时机：

或者 发生miss时
或者 发生hit，但是hit的entry是预取上来的
当 页表2MB的level命中
当 预取项不跨2MB项对应的4KB page frame

前面两个限制是为了限制预取的数量

后面两个限制是限制预取请求只会访问最后一级页表

l2tlb: add next-line prefetcher (#1108)

预取时机：

或者 发生miss时
或者 发生hit，但是hit的entry是预取上来的
当 页表2MB的level命中
当 预取项不跨2MB项对应的4KB page frame

前面两个限制是为了限制预取的数量

后面两个限制是限制预取请求只会访问最后一级页表 -› 不占用FSM & （几乎）不会重新访问cache，造成卡死。

=============
some workloads: gcc(5.4%), wrf(13.6%),milc(9.2%)'s ipc increase.
some workloads decrease: namd(-2.5%).
but l2tlb's perf counters are better.
So I think it is worthy to adding the simple next-line prefetch.

The workloads are of ci and in cold-start state, so prefetch may seems to be much better than it should be.
But l2tlb's memory access ability is much better than what it needs, so the prefetch can be added.
=============

* mmu.l2tlb: add params filterSize

* mmu.l2tlb: add prefetch,dont work well

* mmu.l2tlb: add prefetch relative perf counter

* l2tlb: prefetch recv miss req and 'hit but pre-fetched' req

* l2tlb: fix some perf counter about prefetch

* l2tlb: prefetch not cross 2MB && not recv when 2MB level miss

* ci: when error, copy emu and SimTop.v to WAVE_HOME

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Merge branch 'master' into fix-lightSSS

pmp: add pmp support (#1092)

* [WIP] PMP: add pmp to tlb & csr(ptw part is not added)

* pmp: add pmp, unified

* pmp: add pmp, distributed but same cycle

* pmp: pmp resp next cycle

* [WIP

pmp: add pmp support (#1092)

* [WIP] PMP: add pmp to tlb & csr(ptw part is not added)

* pmp: add pmp, unified

* pmp: add pmp, distributed but same cycle

* pmp: pmp resp next cycle

* [WIP] PMP: add l2tlb missqueue pmp support

* pmp: add pmp to ptw and regnext pmp for frontend

* pmp: fix bug of napot-match

* pmp: fix bug of method aligned

* pmp: when write cfg, update mask

* pmp: fix bug of store af getting in store unit

* tlb: fix bug, add af check(access fault from ptw)

* tlb: af may have higher priority than pf when ptw has af

* ptw: fix bug of sending paddr to pmp and recv af

* ci: add pmp unit test

* pmp: change PMPPlatformGrain to 6 (512bits)

* pmp: fix bug of read_addr

* ci: re-add pmp unit test

* l2tlb: lazymodule couldn't use @chiselName

* l2tlb: fix bug of l2tlb missqueue duplicate req's logic

filt the duplicate req:
old: when enq, change enq state to different state
new: enq + mem.req.fire, more robust

* pmp: pmp checker now supports samecycle & regenable

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script: add wave dump path

Merge branch 'master' into fix-lightSSS

add softprefetch (prefetch.r & prefetch.w). (#1099)

* add soft prefetch
Add the softprefetch. Actually, prefetch.r&w are an ORI which's ldest is x0, we distinguish it in decodeUnit and send it to l

add softprefetch (prefetch.r & prefetch.w). (#1099)

* add soft prefetch
Add the softprefetch. Actually, prefetch.r&w are an ORI which's ldest is x0, we distinguish it in decodeUnit and send it to ld func unit. Then, we modified some interaction signals in ordinary Load steps.

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riscv-crypto: support K extension (#1102)

* This commit add risc-v cryptography extension subset(zknd zkne zknh zksed zksh)
- Rename bmu to bku
- Add crypto instruction in Mdu -> bku
- Store imme

riscv-crypto: support K extension (#1102)

* This commit add risc-v cryptography extension subset(zknd zkne zknh zksed zksh)
- Rename bmu to bku
- Add crypto instruction in Mdu -> bku
- Store immediate into mdu RS

* ci: add riscv-crypto test

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