1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18import utils._ 19import chisel3._ 20import chisel3.util._ 21import chipsalliance.rocketchip.config.Parameters 22import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 23import xiangshan._ 24import xiangshan.cache._ 25import xiangshan.frontend.icache._ 26import xiangshan.cache.mmu.{TlbRequestIO, TlbPtwIO,TLB} 27import xiangshan.backend.fu.{HasExceptionNO, PMP, PMPChecker, PFEvent} 28 29 30class Frontend()(implicit p: Parameters) extends LazyModule with HasXSParameter{ 31 32 val instrUncache = LazyModule(new InstrUncache()) 33 val icache = LazyModule(new ICache()) 34 35 lazy val module = new FrontendImp(this) 36} 37 38 39class FrontendImp (outer: Frontend) extends LazyModuleImp(outer) 40 with HasXSParameter 41 with HasExceptionNO 42{ 43 val io = IO(new Bundle() { 44 val fencei = Input(Bool()) 45 val ptw = new TlbPtwIO(2) 46 val backend = new FrontendToCtrlIO 47 val sfence = Input(new SfenceBundle) 48 val tlbCsr = Input(new TlbCsrBundle) 49 val csrCtrl = Input(new CustomCSRCtrlIO) 50 val csrUpdate = new DistributedCSRUpdateReq 51 val error = new L1CacheErrorInfo 52 val frontendInfo = new Bundle { 53 val ibufFull = Output(Bool()) 54 val bpuInfo = new Bundle { 55 val bpRight = Output(UInt(XLEN.W)) 56 val bpWrong = Output(UInt(XLEN.W)) 57 } 58 } 59 }) 60 61 //decouped-frontend modules 62 val instrUncache = outer.instrUncache.module 63 val icache = outer.icache.module 64 val bpu = Module(new Predictor) 65 val ifu = Module(new NewIFU) 66 val ibuffer = Module(new Ibuffer) 67 val ftq = Module(new Ftq) 68 69 //PFEvent 70 val pfevent = Module(new PFEvent) 71 val tlbCsr = RegNext(io.tlbCsr) 72 pfevent.io.distribute_csr := io.csrCtrl.distribute_csr 73 74 // trigger 75 ifu.io.frontendTrigger := io.csrCtrl.frontend_trigger 76 val triggerEn = io.csrCtrl.trigger_enable 77 ifu.io.csrTriggerEnable := VecInit(triggerEn(0), triggerEn(1), triggerEn(6), triggerEn(8)) 78 79 // pmp 80 val pmp = Module(new PMP()) 81 val pmp_check = VecInit(Seq.fill(2)(Module(new PMPChecker(3, sameCycle = true)).io)) 82 pmp.io.distribute_csr := io.csrCtrl.distribute_csr 83 for (i <- pmp_check.indices) { 84 pmp_check(i).env.pmp := pmp.io.pmp 85 pmp_check(i).env.pma := pmp.io.pma 86 pmp_check(i).env.mode := tlbCsr.priv.imode 87 pmp_check(i).req <> icache.io.pmp(i).req 88 icache.io.pmp(i).resp <> pmp_check(i).resp 89 } 90 91 io.ptw <> TLB( 92 in = Seq(icache.io.itlb(0), icache.io.itlb(1)), 93 sfence = io.sfence, 94 csr = tlbCsr, 95 width = 2, 96 shouldBlock = true, 97 itlbParams 98 ) 99 100 icache.io.fencei := RegNext(io.fencei) 101 102 val needFlush = io.backend.toFtq.stage3Redirect.valid 103 104 //IFU-Ftq 105 ifu.io.ftqInter.fromFtq <> ftq.io.toIfu 106 ftq.io.fromIfu <> ifu.io.ftqInter.toFtq 107 bpu.io.ftq_to_bpu <> ftq.io.toBpu 108 ftq.io.fromBpu <> bpu.io.bpu_to_ftq 109 //IFU-ICache 110 for(i <- 0 until 2){ 111 ifu.io.icacheInter(i).req <> icache.io.fetch(i).req 112 icache.io.fetch(i).req <> ifu.io.icacheInter(i).req 113 ifu.io.icacheInter(i).resp <> icache.io.fetch(i).resp 114 } 115 icache.io.stop := ifu.io.icacheStop 116 117 ifu.io.icachePerfInfo := icache.io.perfInfo 118 119 //icache.io.missQueue.flush := ifu.io.ftqInter.fromFtq.redirect.valid || (ifu.io.ftqInter.toFtq.pdWb.valid && ifu.io.ftqInter.toFtq.pdWb.bits.misOffset.valid) 120 121 icache.io.csr.distribute_csr <> io.csrCtrl.distribute_csr 122 icache.io.csr.update <> io.csrUpdate 123 124 //IFU-Ibuffer 125 ifu.io.toIbuffer <> ibuffer.io.in 126 127 ftq.io.fromBackend <> io.backend.toFtq 128 io.backend.fromFtq <> ftq.io.toBackend 129 io.frontendInfo.bpuInfo <> ftq.io.bpuInfo 130 131 ifu.io.rob_commits <> io.backend.toFtq.rob_commits 132 133 ibuffer.io.flush := needFlush 134 io.backend.cfVec <> ibuffer.io.out 135 136 instrUncache.io.req <> ifu.io.uncacheInter.toUncache 137 ifu.io.uncacheInter.fromUncache <> instrUncache.io.resp 138 instrUncache.io.flush := false.B//icache.io.missQueue.flush 139 io.error <> DontCare 140 141 val frontendBubble = PopCount((0 until DecodeWidth).map(i => io.backend.cfVec(i).ready && !ibuffer.io.out(i).valid)) 142 XSPerfAccumulate("FrontendBubble", frontendBubble) 143 io.frontendInfo.ibufFull := RegNext(ibuffer.io.full) 144 145 if(print_perfcounter){ 146 val ifu_perf = ifu.perfEvents.map(_._1).zip(ifu.perfinfo.perfEvents.perf_events) 147 val ibuffer_perf = ibuffer.perfEvents.map(_._1).zip(ibuffer.perfinfo.perfEvents.perf_events) 148 val icache_perf = icache.perfEvents.map(_._1).zip(icache.perfinfo.perfEvents.perf_events) 149 val ftq_perf = ftq.perfEvents.map(_._1).zip(ftq.perfinfo.perfEvents.perf_events) 150 val bpu_perf = bpu.perfEvents.map(_._1).zip(bpu.perfinfo.perfEvents.perf_events) 151 val perfEvents = ifu_perf ++ ibuffer_perf ++ icache_perf ++ ftq_perf ++ bpu_perf 152 153 for (((perf_name,perf),i) <- perfEvents.zipWithIndex) { 154 println(s"frontend perf $i: $perf_name") 155 } 156 } 157 158 val hpmEvents = ifu.perfinfo.perfEvents.perf_events ++ ibuffer.perfinfo.perfEvents.perf_events ++ 159 icache.perfinfo.perfEvents.perf_events ++ ftq.perfinfo.perfEvents.perf_events ++ 160 bpu.perfinfo.perfEvents.perf_events 161 val perf_length = hpmEvents.length 162 val csrevents = pfevent.io.hpmevent.slice(0,8) 163 val perfinfo = IO(new Bundle(){ 164 val perfEvents = Output(new PerfEventsBundle(csrevents.length)) 165 }) 166 val hpm_frontend = Module(new HPerfmonitor(perf_length,csrevents.length)) 167 hpm_frontend.io.hpm_event := csrevents 168 hpm_frontend.io.events_sets.perf_events := hpmEvents 169 perfinfo.perfEvents := RegNext(hpm_frontend.io.events_selected) 170} 171