L2TLB.scala (d2b20d1a96e238e36a849bd253f65ec7b6a5db38) L2TLB.scala (7d45a146d3c44839ba821bb91ca4950dc2b817f2)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 295 unchanged lines hidden (view full) ---

304 cache.io.refill.bits.sel_pte_dup.map(_ := RegNext(sel_data(refill_data_tmp.asUInt, req_addr_low(mem.d.bits.source))))
305
306 if (env.EnableDifftest) {
307 val difftest_ptw_addr = RegInit(VecInit(Seq.fill(MemReqWidth)(0.U(PAddrBits.W))))
308 when (mem.a.valid) {
309 difftest_ptw_addr(mem.a.bits.source) := mem.a.bits.address
310 }
311
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 295 unchanged lines hidden (view full) ---

304 cache.io.refill.bits.sel_pte_dup.map(_ := RegNext(sel_data(refill_data_tmp.asUInt, req_addr_low(mem.d.bits.source))))
305
306 if (env.EnableDifftest) {
307 val difftest_ptw_addr = RegInit(VecInit(Seq.fill(MemReqWidth)(0.U(PAddrBits.W))))
308 when (mem.a.valid) {
309 difftest_ptw_addr(mem.a.bits.source) := mem.a.bits.address
310 }
311
312 val difftest = Module(new DifftestRefillEvent)
313 difftest.io.clock := clock
314 difftest.io.coreid := p(XSCoreParamsKey).HartId.asUInt
315 difftest.io.cacheid := 2.U
316 difftest.io.valid := cache.io.refill.valid
317 difftest.io.addr := difftest_ptw_addr(RegNext(mem.d.bits.source))
318 difftest.io.data := refill_data.asTypeOf(difftest.io.data)
312 val difftest = DifftestModule(new DiffRefillEvent)
313 difftest.clock := clock
314 difftest.coreid := p(XSCoreParamsKey).HartId.asUInt
315 difftest.index := 2.U
316 difftest.valid := cache.io.refill.valid
317 difftest.addr := difftest_ptw_addr(RegNext(mem.d.bits.source))
318 difftest.data := refill_data.asTypeOf(difftest.data)
319 }
320
321 if (env.EnableDifftest) {
322 for (i <- 0 until PtwWidth) {
319 }
320
321 if (env.EnableDifftest) {
322 for (i <- 0 until PtwWidth) {
323 val difftest = Module(new DifftestL2TLBEvent)
324 difftest.io.clock := clock
325 difftest.io.coreid := p(XSCoreParamsKey).HartId.asUInt
326 difftest.io.valid := io.tlb(i).resp.fire && !io.tlb(i).resp.bits.af
327 difftest.io.index := i.U
328 difftest.io.satp := io.csr.tlb.satp.ppn
329 difftest.io.vpn := Cat(io.tlb(i).resp.bits.entry.tag, 0.U(sectortlbwidth.W))
323 val difftest = DifftestModule(new DiffL2TLBEvent)
324 difftest.clock := clock
325 difftest.coreid := p(XSCoreParamsKey).HartId.asUInt
326 difftest.valid := io.tlb(i).resp.fire && !io.tlb(i).resp.bits.af
327 difftest.index := i.U
328 difftest.satp := io.csr.tlb.satp.ppn
329 difftest.vpn := Cat(io.tlb(i).resp.bits.entry.tag, 0.U(sectortlbwidth.W))
330 for (j <- 0 until tlbcontiguous) {
330 for (j <- 0 until tlbcontiguous) {
331 difftest.io.ppn(j) := Cat(io.tlb(i).resp.bits.entry.ppn, io.tlb(i).resp.bits.ppn_low(j))
332 difftest.io.valididx(j) := io.tlb(i).resp.bits.valididx(j)
331 difftest.ppn(j) := Cat(io.tlb(i).resp.bits.entry.ppn, io.tlb(i).resp.bits.ppn_low(j))
332 difftest.valididx(j) := io.tlb(i).resp.bits.valididx(j)
333 }
333 }
334 difftest.io.perm := io.tlb(i).resp.bits.entry.perm.getOrElse(0.U.asTypeOf(new PtePermBundle)).asUInt
335 difftest.io.level := io.tlb(i).resp.bits.entry.level.getOrElse(0.U.asUInt)
336 difftest.io.pf := io.tlb(i).resp.bits.pf
334 difftest.perm := io.tlb(i).resp.bits.entry.perm.getOrElse(0.U.asTypeOf(new PtePermBundle)).asUInt
335 difftest.level := io.tlb(i).resp.bits.entry.level.getOrElse(0.U.asUInt)
336 difftest.pf := io.tlb(i).resp.bits.pf
337 }
338 }
339
340 // pmp
341 pmp_check(0).req <> ptw.io.pmp.req
342 ptw.io.pmp.resp <> pmp_check(0).resp
343 pmp_check(1).req <> llptw.io.pmp.req
344 llptw.io.pmp.resp <> pmp_check(1).resp

--- 349 unchanged lines hidden --- 		337 }
338 }
339
340 // pmp
341 pmp_check(0).req <> ptw.io.pmp.req
342 ptw.io.pmp.resp <> pmp_check(0).resp
343 pmp_check(1).req <> llptw.io.pmp.req
344 llptw.io.pmp.resp <> pmp_check(1).resp

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