XSTileWrap.scala (4a699e275a42daaf03e4f014bad0bb16d893e6ff) XSTileWrap.scala (4b2c87ba1d7965f6f2b0a396be707a6e2f6fb345)
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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20import chisel3.util._
21import org.chipsalliance.cde.config._
22import freechips.rocketchip.diplomacy._
23import freechips.rocketchip.interrupts._
24import freechips.rocketchip.tilelink._
25import freechips.rocketchip.util._
26import system.HasSoCParameter
27import device.{IMSICAsync, MsiInfoBundle}
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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20import chisel3.util._
21import org.chipsalliance.cde.config._
22import freechips.rocketchip.diplomacy._
23import freechips.rocketchip.interrupts._
24import freechips.rocketchip.tilelink._
25import freechips.rocketchip.util._
26import system.HasSoCParameter
27import device.{IMSICAsync, MsiInfoBundle}
28import coupledL2.tl2chi.{PortIO, AsyncPortIO, CHIAsyncBridgeSource}
29import utility.{IntBuffer, ResetGen}
28import coupledL2.tl2chi.{AsyncPortIO, CHIAsyncBridgeSource, PortIO}
29import utility.sram.SramBroadcastBundle
30import utility.{DFTResetSignals, IntBuffer, ResetGen}
30import xiangshan.backend.trace.TraceCoreInterface
31
32// This module is used for XSNoCTop for async time domain and divide different
33// voltage domain. Everything in this module should be in the core clock domain
34// and higher voltage domain.
35class XSTileWrap()(implicit p: Parameters) extends LazyModule
36 with HasXSParameter
37 with HasSoCParameter

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86 case Some(param) => new AsyncPortIO(param)
87 case None => new PortIO
88 }
89 val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None
90 val clintTime = EnableClintAsyncBridge match {
91 case Some(param) => Flipped(new AsyncBundle(UInt(64.W), param))
92 case None => Input(ValidIO(UInt(64.W)))
93 }
31import xiangshan.backend.trace.TraceCoreInterface
32
33// This module is used for XSNoCTop for async time domain and divide different
34// voltage domain. Everything in this module should be in the core clock domain
35// and higher voltage domain.
36class XSTileWrap()(implicit p: Parameters) extends LazyModule
37 with HasXSParameter
38 with HasSoCParameter

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87 case Some(param) => new AsyncPortIO(param)
88 case None => new PortIO
89 }
90 val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None
91 val clintTime = EnableClintAsyncBridge match {
92 case Some(param) => Flipped(new AsyncBundle(UInt(64.W), param))
93 case None => Input(ValidIO(UInt(64.W)))
94 }
95 val dft = if(hasMbist) Some(Input(new SramBroadcastBundle)) else None
96 val dft_reset = if(hasMbist) Some(Input(new DFTResetSignals())) else None
94 })
95
97 })
98
96 val reset_sync = withClockAndReset(clock, (reset.asBool || io.hartResetReq).asAsyncReset)(ResetGen())
97 val noc_reset_sync = EnableCHIAsyncBridge.map(_ => withClockAndReset(clock, noc_reset.get)(ResetGen()))
98 val soc_reset_sync = withClockAndReset(clock, soc_reset)(ResetGen())
99 val reset_sync = withClockAndReset(clock, (reset.asBool || io.hartResetReq).asAsyncReset)(ResetGen(2, io.dft_reset))
100 val noc_reset_sync = EnableCHIAsyncBridge.map(_ => withClockAndReset(clock, noc_reset.get)(ResetGen(2, io.dft_reset)))
101 val soc_reset_sync = withClockAndReset(clock, soc_reset)(ResetGen(2, io.dft_reset))
99
100 // override LazyRawModuleImp's clock and reset
101 childClock := clock
102 childReset := reset_sync
103
104 val imsicAsync = withClockAndReset(clock, reset_sync)(Module(new IMSICAsync()))
105 imsicAsync.i.msiInfo := io.msiInfo
106
107 tile.module.io.hartId := io.hartId
108 tile.module.io.msiInfo := imsicAsync.o.msiInfo
109 tile.module.io.reset_vector := io.reset_vector
102
103 // override LazyRawModuleImp's clock and reset
104 childClock := clock
105 childReset := reset_sync
106
107 val imsicAsync = withClockAndReset(clock, reset_sync)(Module(new IMSICAsync()))
108 imsicAsync.i.msiInfo := io.msiInfo
109
110 tile.module.io.hartId := io.hartId
111 tile.module.io.msiInfo := imsicAsync.o.msiInfo
112 tile.module.io.reset_vector := io.reset_vector
113 tile.module.io.dft.zip(io.dft).foreach({case(a, b) => a := b})
114 tile.module.io.dft_reset.zip(io.dft_reset).foreach({case(a, b) => a := b})
110 io.cpu_halt := tile.module.io.cpu_halt
111 io.cpu_crtical_error := tile.module.io.cpu_crtical_error
112 io.hartIsInReset := tile.module.io.hartIsInReset
113 io.traceCoreInterface <> tile.module.io.traceCoreInterface
114 io.debugTopDown <> tile.module.io.debugTopDown
115 tile.module.io.l3Miss := io.l3Miss
116 tile.module.io.nodeID.foreach(_ := io.nodeID.get)
117

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143 dmAsyncSourceOpt.get.module.clock := clock
144 dmAsyncSourceOpt.get.module.reset := soc_reset_sync
145 }
146
147 withClockAndReset(clock, reset_sync) {
148 // Modules are reset one by one
149 // reset ----> SYNC --> XSTile
150 val resetChain = Seq(Seq(tile.module))
115 io.cpu_halt := tile.module.io.cpu_halt
116 io.cpu_crtical_error := tile.module.io.cpu_crtical_error
117 io.hartIsInReset := tile.module.io.hartIsInReset
118 io.traceCoreInterface <> tile.module.io.traceCoreInterface
119 io.debugTopDown <> tile.module.io.debugTopDown
120 tile.module.io.l3Miss := io.l3Miss
121 tile.module.io.nodeID.foreach(_ := io.nodeID.get)
122

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148 dmAsyncSourceOpt.get.module.clock := clock
149 dmAsyncSourceOpt.get.module.reset := soc_reset_sync
150 }
151
152 withClockAndReset(clock, reset_sync) {
153 // Modules are reset one by one
154 // reset ----> SYNC --> XSTile
155 val resetChain = Seq(Seq(tile.module))
151 ResetGen(resetChain, reset_sync, !debugOpts.FPGAPlatform)
156 ResetGen(resetChain, reset_sync, !debugOpts.FPGAPlatform, io.dft_reset)
152 }
153 dontTouch(io.hartId)
154 dontTouch(io.msiInfo)
155 }
156 lazy val module = new XSTileWrapImp(this)
157}
157 }
158 dontTouch(io.hartId)
159 dontTouch(io.msiInfo)
160 }
161 lazy val module = new XSTileWrapImp(this)
162}