XSTileWrap.scala (42cb64260d34f2b47839d26c7af8b31eef9031c9) XSTileWrap.scala (8cfc24b28454f1915c339ce79485711f8e438f59)
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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19import chisel3._
20import chisel3.util._
21import org.chipsalliance.cde.config._
22import freechips.rocketchip.diplomacy._
23import freechips.rocketchip.interrupts._
24import freechips.rocketchip.tilelink._
25import freechips.rocketchip.util._
26import system.HasSoCParameter
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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19import chisel3._
20import chisel3.util._
21import org.chipsalliance.cde.config._
22import freechips.rocketchip.diplomacy._
23import freechips.rocketchip.interrupts._
24import freechips.rocketchip.tilelink._
25import freechips.rocketchip.util._
26import system.HasSoCParameter
27import device.{IMSICAsync, MsiInfoBundle}
27import device.IMSICAsync
28import coupledL2.tl2chi.{AsyncPortIO, CHIAsyncBridgeSource, PortIO}
29import utility.sram.{SramBroadcastBundle, SramMbistBundle}
30import utility.{DFTResetSignals, IntBuffer, ResetGen}
31import xiangshan.backend.trace.TraceCoreInterface
32
33// This module is used for XSNoCTop for async time domain and divide different
34// voltage domain. Everything in this module should be in the core clock domain
35// and higher voltage domain.

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65
66 class XSTileWrapImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) {
67 val clock = IO(Input(Clock()))
68 val reset = IO(Input(AsyncReset()))
69 val noc_reset = EnableCHIAsyncBridge.map(_ => IO(Input(AsyncReset())))
70 val soc_reset = IO(Input(AsyncReset()))
71 val io = IO(new Bundle {
72 val hartId = Input(UInt(hartIdLen.W))
28import coupledL2.tl2chi.{AsyncPortIO, CHIAsyncBridgeSource, PortIO}
29import utility.sram.{SramBroadcastBundle, SramMbistBundle}
30import utility.{DFTResetSignals, IntBuffer, ResetGen}
31import xiangshan.backend.trace.TraceCoreInterface
32
33// This module is used for XSNoCTop for async time domain and divide different
34// voltage domain. Everything in this module should be in the core clock domain
35// and higher voltage domain.

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65
66 class XSTileWrapImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) {
67 val clock = IO(Input(Clock()))
68 val reset = IO(Input(AsyncReset()))
69 val noc_reset = EnableCHIAsyncBridge.map(_ => IO(Input(AsyncReset())))
70 val soc_reset = IO(Input(AsyncReset()))
71 val io = IO(new Bundle {
72 val hartId = Input(UInt(hartIdLen.W))
73 val msiInfo = Input(ValidIO(new MsiInfoBundle))
73 val msiInfo = Input(ValidIO(UInt(soc.IMSICParams.MSI_INFO_WIDTH.W)))
74 val msiAck = Output(Bool())
74 val reset_vector = Input(UInt(PAddrBits.W))
75 val cpu_halt = Output(Bool())
76 val cpu_crtical_error = Output(Bool())
77 val hartResetReq = Input(Bool())
78 val hartIsInReset = Output(Bool())
79 val traceCoreInterface = new TraceCoreInterface
80 val debugTopDown = new Bundle {
81 val robHeadPaddr = Valid(UInt(PAddrBits.W))

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115 imsicAsync.i.msiInfo := io.msiInfo
116
117 tile.module.io.hartId := io.hartId
118 tile.module.io.msiInfo := imsicAsync.o.msiInfo
119 tile.module.io.reset_vector := io.reset_vector
120 tile.module.io.sramTest := io.sramTest
121 io.cpu_halt := tile.module.io.cpu_halt
122 io.cpu_crtical_error := tile.module.io.cpu_crtical_error
75 val reset_vector = Input(UInt(PAddrBits.W))
76 val cpu_halt = Output(Bool())
77 val cpu_crtical_error = Output(Bool())
78 val hartResetReq = Input(Bool())
79 val hartIsInReset = Output(Bool())
80 val traceCoreInterface = new TraceCoreInterface
81 val debugTopDown = new Bundle {
82 val robHeadPaddr = Valid(UInt(PAddrBits.W))

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116 imsicAsync.i.msiInfo := io.msiInfo
117
118 tile.module.io.hartId := io.hartId
119 tile.module.io.msiInfo := imsicAsync.o.msiInfo
120 tile.module.io.reset_vector := io.reset_vector
121 tile.module.io.sramTest := io.sramTest
122 io.cpu_halt := tile.module.io.cpu_halt
123 io.cpu_crtical_error := tile.module.io.cpu_crtical_error
124 io.msiAck := tile.module.io.msiAck
123 io.hartIsInReset := tile.module.io.hartIsInReset
124 io.traceCoreInterface <> tile.module.io.traceCoreInterface
125 io.debugTopDown <> tile.module.io.debugTopDown
126 tile.module.io.l3Miss := io.l3Miss
127 tile.module.io.nodeID.foreach(_ := io.nodeID.get)
128 io.l2_flush_en.foreach { _ := tile.module.io.l2_flush_en.getOrElse(false.B) }
129 io.l2_flush_done.foreach { _ := tile.module.io.l2_flush_done.getOrElse(false.B) }
130 io.pwrdown_ack_n.foreach { _ := true.B }

--- 41 unchanged lines hidden --- 		125 io.hartIsInReset := tile.module.io.hartIsInReset
126 io.traceCoreInterface <> tile.module.io.traceCoreInterface
127 io.debugTopDown <> tile.module.io.debugTopDown
128 tile.module.io.l3Miss := io.l3Miss
129 tile.module.io.nodeID.foreach(_ := io.nodeID.get)
130 io.l2_flush_en.foreach { _ := tile.module.io.l2_flush_en.getOrElse(false.B) }
131 io.l2_flush_done.foreach { _ := tile.module.io.l2_flush_done.getOrElse(false.B) }
132 io.pwrdown_ack_n.foreach { _ := true.B }

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