Makefile (cf7d6b7a1a781c73aeb87de112de2e7fe5ea3b7c) Makefile (c92e74ddf7ceb9648d33722f672985bbe0351ee9)
1#***************************************************************************************
2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
4# Copyright (c) 2020-2021 Peng Cheng Laboratory
5#
6# XiangShan is licensed under Mulan PSL v2.
7# You can use this software according to the terms and conditions of the Mulan PSL v2.
8# You may obtain a copy of Mulan PSL v2 at:

--- 23 unchanged lines hidden (view full) ---

32TEST_FILE = $(shell find ./src/test/scala -name '*.scala')
33
34MEM_GEN = ./scripts/vlsi_mem_gen
35MEM_GEN_SEP = ./scripts/gen_sep_mem.sh
36
37CONFIG ?= DefaultConfig
38NUM_CORES ?= 1
39ISSUE ?= E.b
1#***************************************************************************************
2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
4# Copyright (c) 2020-2021 Peng Cheng Laboratory
5#
6# XiangShan is licensed under Mulan PSL v2.
7# You can use this software according to the terms and conditions of the Mulan PSL v2.
8# You may obtain a copy of Mulan PSL v2 at:

--- 23 unchanged lines hidden (view full) ---

32TEST_FILE = $(shell find ./src/test/scala -name '*.scala')
33
34MEM_GEN = ./scripts/vlsi_mem_gen
35MEM_GEN_SEP = ./scripts/gen_sep_mem.sh
36
37CONFIG ?= DefaultConfig
38NUM_CORES ?= 1
39ISSUE ?= E.b
40CHISEL_TARGET ?= systemverilog
40
41SUPPORT_CHI_ISSUE = B E.b
42ifeq ($(findstring $(ISSUE), $(SUPPORT_CHI_ISSUE)),)
43$(error "Unsupported CHI issue: $(ISSUE)")
44endif
45
46ifneq ($(shell echo "$(MAKECMDGOALS)" | grep ' '),)
47$(error At most one target can be specified)
48endif
49
50ifeq ($(MAKECMDGOALS),)
51GOALS = verilog
52else
53GOALS = $(MAKECMDGOALS)
54endif
55
56# common chisel args
57FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf"
58SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf"
41
42SUPPORT_CHI_ISSUE = B E.b
43ifeq ($(findstring $(ISSUE), $(SUPPORT_CHI_ISSUE)),)
44$(error "Unsupported CHI issue: $(ISSUE)")
45endif
46
47ifneq ($(shell echo "$(MAKECMDGOALS)" | grep ' '),)
48$(error At most one target can be specified)
49endif
50
51ifeq ($(MAKECMDGOALS),)
52GOALS = verilog
53else
54GOALS = $(MAKECMDGOALS)
55endif
56
57# common chisel args
58FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf"
59SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf"
59MFC_ARGS = --dump-fir --target systemverilog --split-verilog \
60MFC_ARGS = --dump-fir --target $(CHISEL_TARGET) --split-verilog \
60 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none"
61RELEASE_ARGS += $(MFC_ARGS)
62DEBUG_ARGS += $(MFC_ARGS)
63PLDM_ARGS += $(MFC_ARGS)
64
65ifneq ($(XSTOP_PREFIX),)
66RELEASE_ARGS += --xstop-prefix $(XSTOP_PREFIX)
67DEBUG_ARGS += --xstop-prefix $(XSTOP_PREFIX)

--- 78 unchanged lines hidden (view full) ---

146test-jar:
147 mill -i xiangshan.test.assembly
148
149$(TOP_V): $(SCALA_FILE)
150 mkdir -p $(@D)
151 $(TIME_CMD) mill -i xiangshan.runMain $(FPGATOP) \
152 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS) \
153 --num-cores $(NUM_CORES) $(RELEASE_ARGS)
61 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none"
62RELEASE_ARGS += $(MFC_ARGS)
63DEBUG_ARGS += $(MFC_ARGS)
64PLDM_ARGS += $(MFC_ARGS)
65
66ifneq ($(XSTOP_PREFIX),)
67RELEASE_ARGS += --xstop-prefix $(XSTOP_PREFIX)
68DEBUG_ARGS += --xstop-prefix $(XSTOP_PREFIX)

--- 78 unchanged lines hidden (view full) ---

147test-jar:
148 mill -i xiangshan.test.assembly
149
150$(TOP_V): $(SCALA_FILE)
151 mkdir -p $(@D)
152 $(TIME_CMD) mill -i xiangshan.runMain $(FPGATOP) \
153 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS) \
154 --num-cores $(NUM_CORES) $(RELEASE_ARGS)
155ifeq ($(CHISEL_TARGET),systemverilog)
154 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)"
155 @git log -n 1 >> .__head__
156 @git diff >> .__diff__
157 @sed -i 's/^/\/\// ' .__head__
158 @sed -i 's/^/\/\//' .__diff__
159 @cat .__head__ .__diff__ $@ > .__out__
160 @mv .__out__ $@
161 @rm .__head__ .__diff__
156 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)"
157 @git log -n 1 >> .__head__
158 @git diff >> .__diff__
159 @sed -i 's/^/\/\// ' .__head__
160 @sed -i 's/^/\/\//' .__diff__
161 @cat .__head__ .__diff__ $@ > .__out__
162 @mv .__out__ $@
163 @rm .__head__ .__diff__
164endif
162
163verilog: $(TOP_V)
164
165$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
166 mkdir -p $(@D)
167 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG)
168 @date -R | tee -a $(TIMELOG)
169 $(TIME_CMD) mill -i xiangshan.test.runMain $(SIMTOP) \
170 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(SIM_MEM_ARGS) \
171 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace
165
166verilog: $(TOP_V)
167
168$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
169 mkdir -p $(@D)
170 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG)
171 @date -R | tee -a $(TIMELOG)
172 $(TIME_CMD) mill -i xiangshan.test.runMain $(SIMTOP) \
173 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(SIM_MEM_ARGS) \
174 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace
175ifeq ($(CHISEL_TARGET),systemverilog)
172 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)"
173 @git log -n 1 >> .__head__
174 @git diff >> .__diff__
175 @sed -i 's/^/\/\// ' .__head__
176 @sed -i 's/^/\/\//' .__diff__
177 @cat .__head__ .__diff__ $@ > .__out__
178 @mv .__out__ $@
179 @rm .__head__ .__diff__
180ifeq ($(PLDM),1)
181 sed -i -e 's/$$fatal/$$finish/g' $(RTL_DIR)/*.$(RTL_SUFFIX)
182 sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(RTL_DIR)/*.$(RTL_SUFFIX)
183else
184ifeq ($(ENABLE_XPROP),1)
185 sed -i -e "s/\$$fatal/assert(1\'b0)/g" $(RTL_DIR)/*.$(RTL_SUFFIX)
186else
187 sed -i -e 's/$$fatal/xs_assert_v2(`__FILE__, `__LINE__)/g' $(RTL_DIR)/*.$(RTL_SUFFIX)
188endif
189endif
190 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(RTL_DIR)/*.$(RTL_SUFFIX)
176 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)"
177 @git log -n 1 >> .__head__
178 @git diff >> .__diff__
179 @sed -i 's/^/\/\// ' .__head__
180 @sed -i 's/^/\/\//' .__diff__
181 @cat .__head__ .__diff__ $@ > .__out__
182 @mv .__out__ $@
183 @rm .__head__ .__diff__
184ifeq ($(PLDM),1)
185 sed -i -e 's/$$fatal/$$finish/g' $(RTL_DIR)/*.$(RTL_SUFFIX)
186 sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(RTL_DIR)/*.$(RTL_SUFFIX)
187else
188ifeq ($(ENABLE_XPROP),1)
189 sed -i -e "s/\$$fatal/assert(1\'b0)/g" $(RTL_DIR)/*.$(RTL_SUFFIX)
190else
191 sed -i -e 's/$$fatal/xs_assert_v2(`__FILE__, `__LINE__)/g' $(RTL_DIR)/*.$(RTL_SUFFIX)
192endif
193endif
194 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(RTL_DIR)/*.$(RTL_SUFFIX)
195endif
191
192sim-verilog: $(SIM_TOP_V)
193
194clean:
195 $(MAKE) -C ./difftest clean
196 rm -rf $(BUILD_DIR)
197
198init:

--- 48 unchanged lines hidden --- 		196
197sim-verilog: $(SIM_TOP_V)
198
199clean:
200 $(MAKE) -C ./difftest clean
201 rm -rf $(BUILD_DIR)
202
203init:

--- 48 unchanged lines hidden ---