1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: 9# http://license.coscl.org.cn/MulanPSL2 10# 11# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14# 15# See the Mulan PSL v2 for more details. 16#*************************************************************************************** 17 18BUILD_DIR = ./build 19RTL_DIR = $(BUILD_DIR)/rtl 20 21TOP = $(XSTOP_PREFIX)XSTop 22SIM_TOP = SimTop 23 24FPGATOP = top.TopMain 25SIMTOP = top.SimTop 26 27RTL_SUFFIX ?= sv 28TOP_V = $(RTL_DIR)/$(TOP).$(RTL_SUFFIX) 29SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX) 30 31SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 32TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 33 34MEM_GEN = ./scripts/vlsi_mem_gen 35MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 36 37CONFIG ?= DefaultConfig 38NUM_CORES ?= 1 39ISSUE ?= E.b 40CHISEL_TARGET ?= systemverilog 41 42SUPPORT_CHI_ISSUE = B E.b 43ifeq ($(findstring $(ISSUE), $(SUPPORT_CHI_ISSUE)),) 44$(error "Unsupported CHI issue: $(ISSUE)") 45endif 46 47ifneq ($(shell echo "$(MAKECMDGOALS)" | grep ' '),) 48$(error At most one target can be specified) 49endif 50 51ifeq ($(MAKECMDGOALS),) 52GOALS = verilog 53else 54GOALS = $(MAKECMDGOALS) 55endif 56 57# common chisel args 58FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf" 59SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf" 60MFC_ARGS = --dump-fir --target $(CHISEL_TARGET) --split-verilog \ 61 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" 62RELEASE_ARGS += $(MFC_ARGS) 63DEBUG_ARGS += $(MFC_ARGS) 64PLDM_ARGS += $(MFC_ARGS) 65 66ifneq ($(XSTOP_PREFIX),) 67RELEASE_ARGS += --xstop-prefix $(XSTOP_PREFIX) 68DEBUG_ARGS += --xstop-prefix $(XSTOP_PREFIX) 69PLDM_ARGS += --xstop-prefix $(XSTOP_PREFIX) 70endif 71 72ifeq ($(IMSIC_USE_TL),1) 73RELEASE_ARGS += --imsic-use-tl 74DEBUG_ARGS += --imsic-use-tl 75PLDM_ARGS += --imsic-use-tl 76endif 77 78# co-simulation with DRAMsim3 79ifeq ($(WITH_DRAMSIM3),1) 80ifndef DRAMSIM3_HOME 81$(error DRAMSIM3_HOME is not set) 82endif 83override SIM_ARGS += --with-dramsim3 84endif 85 86# run emu with chisel-db 87ifeq ($(WITH_CHISELDB),1) 88override SIM_ARGS += --with-chiseldb 89endif 90 91# run emu with chisel-db 92ifeq ($(WITH_ROLLINGDB),1) 93override SIM_ARGS += --with-rollingdb 94endif 95 96# enable ResetGen 97ifeq ($(WITH_RESETGEN),1) 98override SIM_ARGS += --reset-gen 99endif 100 101# run with disable all perf 102ifeq ($(DISABLE_PERF),1) 103override SIM_ARGS += --disable-perf 104endif 105 106# run with disable all db 107ifeq ($(DISABLE_ALWAYSDB),1) 108override SIM_ARGS += --disable-alwaysdb 109endif 110 111# dynamic switch CONSTANTIN 112ifeq ($(WITH_CONSTANTIN),1) 113override SIM_ARGS += --with-constantin 114endif 115 116# emu for the release version 117RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen --firtool-opt --ignore-read-enable-mem 118DEBUG_ARGS += --enable-difftest 119PLDM_ARGS += --fpga-platform --enable-difftest 120ifeq ($(RELEASE),1) 121override SIM_ARGS += $(RELEASE_ARGS) 122else ifeq ($(PLDM),1) 123override SIM_ARGS += $(PLDM_ARGS) 124else 125override SIM_ARGS += $(DEBUG_ARGS) 126endif 127 128TIMELOG = $(BUILD_DIR)/time.log 129TIME_CMD = time -avp -o $(TIMELOG) 130 131ifeq ($(PLDM),1) 132SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 133SED_ENDIF = `endif // not def SYNTHESIS 134endif 135 136.DEFAULT_GOAL = verilog 137 138help: 139 mill -i xiangshan.runMain $(FPGATOP) --help 140 141version: 142 mill -i xiangshan.runMain $(FPGATOP) --version 143 144jar: 145 mill -i xiangshan.assembly 146 147test-jar: 148 mill -i xiangshan.test.assembly 149 150$(TOP_V): $(SCALA_FILE) 151 mkdir -p $(@D) 152 $(TIME_CMD) mill -i xiangshan.runMain $(FPGATOP) \ 153 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS) \ 154 --num-cores $(NUM_CORES) $(RELEASE_ARGS) 155ifeq ($(CHISEL_TARGET),systemverilog) 156 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 157 @git log -n 1 >> .__head__ 158 @git diff >> .__diff__ 159 @sed -i 's/^/\/\// ' .__head__ 160 @sed -i 's/^/\/\//' .__diff__ 161 @cat .__head__ .__diff__ $@ > .__out__ 162 @mv .__out__ $@ 163 @rm .__head__ .__diff__ 164endif 165 166verilog: $(TOP_V) 167 168$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 169 mkdir -p $(@D) 170 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG) 171 @date -R | tee -a $(TIMELOG) 172 $(TIME_CMD) mill -i xiangshan.test.runMain $(SIMTOP) \ 173 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(SIM_MEM_ARGS) \ 174 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 175ifeq ($(CHISEL_TARGET),systemverilog) 176 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 177 @git log -n 1 >> .__head__ 178 @git diff >> .__diff__ 179 @sed -i 's/^/\/\// ' .__head__ 180 @sed -i 's/^/\/\//' .__diff__ 181 @cat .__head__ .__diff__ $@ > .__out__ 182 @mv .__out__ $@ 183 @rm .__head__ .__diff__ 184ifeq ($(PLDM),1) 185 sed -i -e 's/$$fatal/$$finish/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 186 sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(RTL_DIR)/*.$(RTL_SUFFIX) 187else 188ifeq ($(ENABLE_XPROP),1) 189 sed -i -e "s/\$$fatal/assert(1\'b0)/g" $(RTL_DIR)/*.$(RTL_SUFFIX) 190else 191 sed -i -e 's/$$fatal/xs_assert_v2(`__FILE__, `__LINE__)/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 192endif 193endif 194 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(RTL_DIR)/*.$(RTL_SUFFIX) 195endif 196 197sim-verilog: $(SIM_TOP_V) 198 199clean: 200 $(MAKE) -C ./difftest clean 201 rm -rf $(BUILD_DIR) 202 203init: 204 git submodule update --init 205 cd rocket-chip && git submodule update --init cde hardfloat 206 cd openLLC && git submodule update --init openNCB 207 208bump: 209 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 210 211bsp: 212 mill -i mill.bsp.BSP/install 213 214idea: 215 mill -i mill.idea.GenIdea/idea 216 217check-format: 218 mill xiangshan.checkFormat 219 220reformat: 221 mill xiangshan.reformat 222 223# verilator simulation 224emu: sim-verilog 225 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 226 227emu-run: emu 228 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 229 230# vcs simulation 231simv: sim-verilog 232 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 233 234simv-run: 235 $(MAKE) -C ./difftest simv-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 236 237# palladium simulation 238pldm-build: sim-verilog 239 $(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 240 241pldm-run: 242 $(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 243 244pldm-debug: 245 $(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 246 247include Makefile.test 248 249include src/main/scala/device/standalone/standalone_device.mk 250 251.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 252