Makefile (afbe002e3432238603f2e4de09345aba9a4510ca) Makefile (45f43e6e5f88874a7573ff096d1e5c2855bd16c7)
1#***************************************************************************************
2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3# Copyright (c) 2020-2021 Peng Cheng Laboratory
4#
5# XiangShan is licensed under Mulan PSL v2.
6# You can use this software according to the terms and conditions of the Mulan PSL v2.
7# You may obtain a copy of Mulan PSL v2 at:
8# http://license.coscl.org.cn/MulanPSL2
9#
10# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13#
14# See the Mulan PSL v2 for more details.
15#***************************************************************************************
16
17BUILD_DIR = ./build
1#***************************************************************************************
2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3# Copyright (c) 2020-2021 Peng Cheng Laboratory
4#
5# XiangShan is licensed under Mulan PSL v2.
6# You can use this software according to the terms and conditions of the Mulan PSL v2.
7# You may obtain a copy of Mulan PSL v2 at:
8# http://license.coscl.org.cn/MulanPSL2
9#
10# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13#
14# See the Mulan PSL v2 for more details.
15#***************************************************************************************
16
17BUILD_DIR = ./build
18RTL_DIR = $(BUILD_DIR)/rtl
18
19TOP = XSTop
20SIM_TOP = SimTop
21
22FPGATOP = top.TopMain
23SIMTOP = top.SimTop
24
19
20TOP = XSTop
21SIM_TOP = SimTop
22
23FPGATOP = top.TopMain
24SIMTOP = top.SimTop
25
25TOP_V = $(BUILD_DIR)/$(TOP).v
26SIM_TOP_V = $(BUILD_DIR)/$(SIM_TOP).v
26TOP_V = $(RTL_DIR)/$(TOP).v
27SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).v
27
28SCALA_FILE = $(shell find ./src/main/scala -name '*.scala')
29TEST_FILE = $(shell find ./src/test/scala -name '*.scala')
30
31MEM_GEN = ./scripts/vlsi_mem_gen
32MEM_GEN_SEP = ./scripts/gen_sep_mem.sh
33SPLIT_VERILOG = ./scripts/split_verilog.sh
34
35IMAGE ?= temp
36CONFIG ?= DefaultConfig
37NUM_CORES ?= 1
38MFC ?= 0
39
28
29SCALA_FILE = $(shell find ./src/main/scala -name '*.scala')
30TEST_FILE = $(shell find ./src/test/scala -name '*.scala')
31
32MEM_GEN = ./scripts/vlsi_mem_gen
33MEM_GEN_SEP = ./scripts/gen_sep_mem.sh
34SPLIT_VERILOG = ./scripts/split_verilog.sh
35
36IMAGE ?= temp
37CONFIG ?= DefaultConfig
38NUM_CORES ?= 1
39MFC ?= 0
40
40# firtool check and download
41FIRTOOL_VERSION = 1.61.0
42FIRTOOL_URL = https://github.com/llvm/circt/releases/download/firtool-$(FIRTOOL_VERSION)/firrtl-bin-linux-x64.tar.gz
43FIRTOOL_PATH = $(shell which firtool 2>/dev/null)
44CACHE_FIRTOOL_PATH = $(HOME)/.cache/xiangshan/firtool-$(FIRTOOL_VERSION)/bin/firtool
45ifeq ($(MFC),1)
46ifeq ($(FIRTOOL_PATH),)
47ifeq ($(wildcard $(CACHE_FIRTOOL_PATH)),)
48$(info [INFO] Firtool not found in your PATH.)
49$(info [INFO] Downloading from $(FIRTOOL_URL))
50$(shell mkdir -p $(HOME)/.cache/xiangshan && curl -L $(FIRTOOL_URL) | tar -xzC $(HOME)/.cache/xiangshan)
51endif
52FIRTOOL_ARGS = --firtool-binary-path $(CACHE_FIRTOOL_PATH)
53endif
54endif
55
56# common chisel args
57ifeq ($(MFC),1)
58CHISEL_VERSION = chisel
59FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).v.conf"
60SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).v.conf"
41# common chisel args
42ifeq ($(MFC),1)
43CHISEL_VERSION = chisel
44FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).v.conf"
45SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).v.conf"
61MFC_ARGS = --dump-fir $(FIRTOOL_ARGS) \
62 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none"
46MFC_ARGS = --dump-fir \
47 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing"
63RELEASE_ARGS += $(MFC_ARGS)
64DEBUG_ARGS += $(MFC_ARGS)
65PLDM_ARGS += $(MFC_ARGS)
66else
67CHISEL_VERSION = chisel3
68FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
69SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
70endif

--- 19 unchanged lines hidden (view full) ---

90# dynamic switch CONSTANTIN
91ifeq ($(WITH_CONSTANTIN),0)
92$(info disable WITH_CONSTANTIN)
93else
94override SIM_ARGS += --with-constantin
95endif
96
97# emu for the release version
48RELEASE_ARGS += $(MFC_ARGS)
49DEBUG_ARGS += $(MFC_ARGS)
50PLDM_ARGS += $(MFC_ARGS)
51else
52CHISEL_VERSION = chisel3
53FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
54SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
55endif

--- 19 unchanged lines hidden (view full) ---

75# dynamic switch CONSTANTIN
76ifeq ($(WITH_CONSTANTIN),0)
77$(info disable WITH_CONSTANTIN)
78else
79override SIM_ARGS += --with-constantin
80endif
81
82# emu for the release version
98RELEASE_ARGS += --fpga-platform --disable-always-basic-diff --disable-perf
83RELEASE_ARGS += --disable-all --remove-assert --fpga-platform
99DEBUG_ARGS += --enable-difftest
100PLDM_ARGS += --disable-all --fpga-platform
101ifeq ($(RELEASE),1)
102override SIM_ARGS += $(RELEASE_ARGS)
103else ifeq ($(PLDM),1)
104override SIM_ARGS += $(PLDM_ARGS)
105else
106override SIM_ARGS += $(DEBUG_ARGS)

--- 10 unchanged lines hidden (view full) ---

117 mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) --help
118
119$(TOP_V): $(SCALA_FILE)
120 mkdir -p $(@D)
121 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) \
122 -td $(@D) --config $(CONFIG) $(FPGA_MEM_ARGS) \
123 --num-cores $(NUM_CORES) $(RELEASE_ARGS)
124ifeq ($(MFC),1)
84DEBUG_ARGS += --enable-difftest
85PLDM_ARGS += --disable-all --fpga-platform
86ifeq ($(RELEASE),1)
87override SIM_ARGS += $(RELEASE_ARGS)
88else ifeq ($(PLDM),1)
89override SIM_ARGS += $(PLDM_ARGS)
90else
91override SIM_ARGS += $(DEBUG_ARGS)

--- 10 unchanged lines hidden (view full) ---

102 mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) --help
103
104$(TOP_V): $(SCALA_FILE)
105 mkdir -p $(@D)
106 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) \
107 -td $(@D) --config $(CONFIG) $(FPGA_MEM_ARGS) \
108 --num-cores $(NUM_CORES) $(RELEASE_ARGS)
109ifeq ($(MFC),1)
125 $(SPLIT_VERILOG) $(BUILD_DIR) $(TOP).v
126 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(BUILD_DIR)"
110 $(SPLIT_VERILOG) $(RTL_DIR) $(TOP).v
111 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(RTL_DIR)"
127endif
128 $(SED_CMD) $@
129 @git log -n 1 >> .__head__
130 @git diff >> .__diff__
131 @sed -i 's/^/\/\// ' .__head__
132 @sed -i 's/^/\/\//' .__diff__
133 @cat .__head__ .__diff__ $@ > .__out__
134 @mv .__out__ $@
135 @rm .__head__ .__diff__
136
137verilog: $(TOP_V)
138
139$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
140 mkdir -p $(@D)
141 @echo "\n[mill] Generating Verilog files..." > $(TIMELOG)
142 @date -R | tee -a $(TIMELOG)
143 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP) \
144 -td $(@D) --config $(CONFIG) $(SIM_MEM_ARGS) \
112endif
113 $(SED_CMD) $@
114 @git log -n 1 >> .__head__
115 @git diff >> .__diff__
116 @sed -i 's/^/\/\// ' .__head__
117 @sed -i 's/^/\/\//' .__diff__
118 @cat .__head__ .__diff__ $@ > .__out__
119 @mv .__out__ $@
120 @rm .__head__ .__diff__
121
122verilog: $(TOP_V)
123
124$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
125 mkdir -p $(@D)
126 @echo "\n[mill] Generating Verilog files..." > $(TIMELOG)
127 @date -R | tee -a $(TIMELOG)
128 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP) \
129 -td $(@D) --config $(CONFIG) $(SIM_MEM_ARGS) \
145 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace
130 --num-cores $(NUM_CORES) $(SIM_ARGS)
146ifeq ($(MFC),1)
131ifeq ($(MFC),1)
147 $(SPLIT_VERILOG) $(BUILD_DIR) $(SIM_TOP).v
148 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(SIM_TOP_V).conf" "$(BUILD_DIR)"
132 $(SPLIT_VERILOG) $(RTL_DIR) $(SIM_TOP).v
133 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(SIM_TOP_V).conf" "$(RTL_DIR)"
149endif
150 $(SED_CMD) $@
151 @git log -n 1 >> .__head__
152 @git diff >> .__diff__
153 @sed -i 's/^/\/\// ' .__head__
154 @sed -i 's/^/\/\//' .__diff__
155 @cat .__head__ .__diff__ $@ > .__out__
156 @mv .__out__ $@

--- 44 unchanged lines hidden --- 		134endif
135 $(SED_CMD) $@
136 @git log -n 1 >> .__head__
137 @git diff >> .__diff__
138 @sed -i 's/^/\/\// ' .__head__
139 @sed -i 's/^/\/\//' .__diff__
140 @cat .__head__ .__diff__ $@ > .__out__
141 @mv .__out__ $@

--- 44 unchanged lines hidden ---