xref: /XiangShan/Makefile (revision 45f43e6e5f88874a7573ff096d1e5c2855bd16c7) 
1#***************************************************************************************
2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3# Copyright (c) 2020-2021 Peng Cheng Laboratory
4#
5# XiangShan is licensed under Mulan PSL v2.
6# You can use this software according to the terms and conditions of the Mulan PSL v2.
7# You may obtain a copy of Mulan PSL v2 at:
8#          http://license.coscl.org.cn/MulanPSL2
9#
10# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13#
14# See the Mulan PSL v2 for more details.
15#***************************************************************************************
16
17BUILD_DIR = ./build
18RTL_DIR = $(BUILD_DIR)/rtl
19
20TOP = XSTop
21SIM_TOP = SimTop
22
23FPGATOP = top.TopMain
24SIMTOP  = top.SimTop
25
26TOP_V = $(RTL_DIR)/$(TOP).v
27SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).v
28
29SCALA_FILE = $(shell find ./src/main/scala -name '*.scala')
30TEST_FILE = $(shell find ./src/test/scala -name '*.scala')
31
32MEM_GEN = ./scripts/vlsi_mem_gen
33MEM_GEN_SEP = ./scripts/gen_sep_mem.sh
34SPLIT_VERILOG = ./scripts/split_verilog.sh
35
36IMAGE  ?= temp
37CONFIG ?= DefaultConfig
38NUM_CORES ?= 1
39MFC ?= 0
40
41# common chisel args
42ifeq ($(MFC),1)
43CHISEL_VERSION = chisel
44FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).v.conf"
45SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).v.conf"
46MFC_ARGS = --dump-fir \
47           --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing"
48RELEASE_ARGS += $(MFC_ARGS)
49DEBUG_ARGS += $(MFC_ARGS)
50PLDM_ARGS += $(MFC_ARGS)
51else
52CHISEL_VERSION = chisel3
53FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
54SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
55endif
56
57# co-simulation with DRAMsim3
58ifeq ($(WITH_DRAMSIM3),1)
59ifndef DRAMSIM3_HOME
60$(error DRAMSIM3_HOME is not set)
61endif
62override SIM_ARGS += --with-dramsim3
63endif
64
65# run emu with chisel-db
66ifeq ($(WITH_CHISELDB),1)
67override SIM_ARGS += --with-chiseldb
68endif
69
70# run emu with chisel-db
71ifeq ($(WITH_ROLLINGDB),1)
72override SIM_ARGS += --with-rollingdb
73endif
74
75# dynamic switch CONSTANTIN
76ifeq ($(WITH_CONSTANTIN),0)
77$(info disable WITH_CONSTANTIN)
78else
79override SIM_ARGS += --with-constantin
80endif
81
82# emu for the release version
83RELEASE_ARGS += --disable-all --remove-assert --fpga-platform
84DEBUG_ARGS   += --enable-difftest
85PLDM_ARGS += --disable-all --fpga-platform
86ifeq ($(RELEASE),1)
87override SIM_ARGS += $(RELEASE_ARGS)
88else ifeq ($(PLDM),1)
89override SIM_ARGS += $(PLDM_ARGS)
90else
91override SIM_ARGS += $(DEBUG_ARGS)
92endif
93
94TIMELOG = $(BUILD_DIR)/time.log
95TIME_CMD = time -a -o $(TIMELOG)
96
97SED_CMD = sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g'
98
99.DEFAULT_GOAL = verilog
100
101help:
102	mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) --help
103
104$(TOP_V): $(SCALA_FILE)
105	mkdir -p $(@D)
106	$(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP)   \
107		-td $(@D) --config $(CONFIG) $(FPGA_MEM_ARGS)                    \
108		--num-cores $(NUM_CORES) $(RELEASE_ARGS)
109ifeq ($(MFC),1)
110	$(SPLIT_VERILOG) $(RTL_DIR) $(TOP).v
111	$(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(RTL_DIR)"
112endif
113	$(SED_CMD) $@
114	@git log -n 1 >> .__head__
115	@git diff >> .__diff__
116	@sed -i 's/^/\/\// ' .__head__
117	@sed -i 's/^/\/\//' .__diff__
118	@cat .__head__ .__diff__ $@ > .__out__
119	@mv .__out__ $@
120	@rm .__head__ .__diff__
121
122verilog: $(TOP_V)
123
124$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
125	mkdir -p $(@D)
126	@echo "\n[mill] Generating Verilog files..." > $(TIMELOG)
127	@date -R | tee -a $(TIMELOG)
128	$(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP)    \
129		-td $(@D) --config $(CONFIG) $(SIM_MEM_ARGS)                          \
130		--num-cores $(NUM_CORES) $(SIM_ARGS)
131ifeq ($(MFC),1)
132	$(SPLIT_VERILOG) $(RTL_DIR) $(SIM_TOP).v
133	$(MEM_GEN_SEP) "$(MEM_GEN)" "$(SIM_TOP_V).conf" "$(RTL_DIR)"
134endif
135	$(SED_CMD) $@
136	@git log -n 1 >> .__head__
137	@git diff >> .__diff__
138	@sed -i 's/^/\/\// ' .__head__
139	@sed -i 's/^/\/\//' .__diff__
140	@cat .__head__ .__diff__ $@ > .__out__
141	@mv .__out__ $@
142	@rm .__head__ .__diff__
143ifeq ($(PLDM),1)
144	sed -i -e 's/$$fatal/$$finish/g' $(SIM_TOP_V)
145	sed -i -e 's|`ifndef SYNTHESIS	// src/main/scala/device/RocketDebugWrapper.scala:141:11|`ifdef SYNTHESIS	// src/main/scala/device/RocketDebugWrapper.scala:141:11|g' $(SIM_TOP_V)
146else
147	sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' $(SIM_TOP_V)
148endif
149ifeq ($(MFC),1)
150	sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(SIM_TOP_V)
151endif
152
153sim-verilog: $(SIM_TOP_V)
154
155clean:
156	$(MAKE) -C ./difftest clean
157	rm -rf $(BUILD_DIR)
158
159init:
160	git submodule update --init
161	cd rocket-chip && git submodule update --init cde hardfloat
162
163bump:
164	git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master"
165
166bsp:
167	mill -i mill.bsp.BSP/install
168
169idea:
170	mill -i mill.scalalib.GenIdea/idea
171
172# verilator simulation
173emu: sim-verilog
174	$(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
175
176emu-run: emu
177	$(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
178
179# vcs simulation
180simv:
181	$(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
182
183include Makefile.test
184
185.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO)
186