1 /* 2 * axi lite register access driver 3 * Author: Xianjun Jiao, Michael Mehari, Wei Liu 4 * SPDX-FileCopyrightText: 2019 UGent 5 * SPDX-License-Identifier: AGPL-3.0-or-later 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/dmapool.h> 10 #include <linux/dma/xilinx_dma.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/of_dma.h> 18 #include <linux/of_platform.h> 19 #include <linux/of_irq.h> 20 #include <linux/slab.h> 21 #include <linux/clk.h> 22 #include <linux/io-64-nonatomic-lo-hi.h> 23 #include <linux/delay.h> 24 #include <net/mac80211.h> 25 26 #include "../hw_def.h" 27 28 static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design 29 30 /* IO accessors */ 31 static inline u32 reg_read(u32 reg) 32 { 33 return ioread32(base_addr + reg); 34 } 35 36 static inline void reg_write(u32 reg, u32 value) 37 { 38 iowrite32(value, base_addr + reg); 39 } 40 41 static inline void XPU_REG_MULTI_RST_write(u32 Data) { 42 reg_write(XPU_REG_MULTI_RST_ADDR, Data); 43 } 44 45 static inline u32 XPU_REG_MULTI_RST_read(void){ 46 return reg_read(XPU_REG_MULTI_RST_ADDR); 47 } 48 49 static inline void XPU_REG_SRC_SEL_write(u32 Data) { 50 reg_write(XPU_REG_SRC_SEL_ADDR, Data); 51 } 52 53 static inline u32 XPU_REG_SRC_SEL_read(void){ 54 return reg_read(XPU_REG_SRC_SEL_ADDR); 55 } 56 57 static inline void XPU_REG_RECV_ACK_COUNT_TOP0_write(u32 Data) { 58 reg_write(XPU_REG_RECV_ACK_COUNT_TOP0_ADDR, Data); 59 } 60 61 static inline u32 XPU_REG_RECV_ACK_COUNT_TOP0_read(void){ 62 return reg_read(XPU_REG_RECV_ACK_COUNT_TOP0_ADDR); 63 } 64 65 static inline void XPU_REG_RECV_ACK_COUNT_TOP1_write(u32 Data) { 66 reg_write(XPU_REG_RECV_ACK_COUNT_TOP1_ADDR, Data); 67 } 68 69 static inline u32 XPU_REG_RECV_ACK_COUNT_TOP1_read(void){ 70 return reg_read(XPU_REG_RECV_ACK_COUNT_TOP1_ADDR); 71 } 72 73 static inline void XPU_REG_SEND_ACK_WAIT_TOP_write(u32 Data) { 74 reg_write(XPU_REG_SEND_ACK_WAIT_TOP_ADDR, Data); 75 } 76 77 static inline u32 XPU_REG_SEND_ACK_WAIT_TOP_read(void){ 78 return reg_read(XPU_REG_SEND_ACK_WAIT_TOP_ADDR); 79 } 80 81 static inline void XPU_REG_FILTER_FLAG_write(u32 Data) { 82 reg_write(XPU_REG_FILTER_FLAG_ADDR, Data); 83 } 84 85 static inline u32 XPU_REG_FILTER_FLAG_read(void){ 86 return reg_read(XPU_REG_FILTER_FLAG_ADDR); 87 } 88 89 static inline void XPU_REG_CTS_TO_RTS_CONFIG_write(u32 Data) { 90 reg_write(XPU_REG_CTS_TO_RTS_CONFIG_ADDR, Data); 91 } 92 93 static inline u32 XPU_REG_CTS_TO_RTS_CONFIG_read(void){ 94 return reg_read(XPU_REG_CTS_TO_RTS_CONFIG_ADDR); 95 } 96 97 static inline void XPU_REG_MAC_ADDR_LOW_write(u32 Data) { 98 reg_write(XPU_REG_MAC_ADDR_LOW_ADDR, Data); 99 } 100 101 static inline u32 XPU_REG_MAC_ADDR_LOW_read(void){ 102 return reg_read(XPU_REG_MAC_ADDR_LOW_ADDR); 103 } 104 105 static inline void XPU_REG_MAC_ADDR_HIGH_write(u32 Data) { 106 reg_write(XPU_REG_MAC_ADDR_HIGH_ADDR, Data); 107 } 108 109 static inline u32 XPU_REG_MAC_ADDR_HIGH_read(void){ 110 return reg_read(XPU_REG_MAC_ADDR_HIGH_ADDR); 111 } 112 113 static inline void XPU_REG_BSSID_FILTER_LOW_write(u32 Data) { 114 reg_write(XPU_REG_BSSID_FILTER_LOW_ADDR, Data); 115 } 116 117 static inline u32 XPU_REG_BSSID_FILTER_LOW_read(void){ 118 return reg_read(XPU_REG_BSSID_FILTER_LOW_ADDR); 119 } 120 121 static inline void XPU_REG_BSSID_FILTER_HIGH_write(u32 Data) { 122 reg_write(XPU_REG_BSSID_FILTER_HIGH_ADDR, Data); 123 } 124 125 static inline u32 XPU_REG_BSSID_FILTER_HIGH_read(void){ 126 return reg_read(XPU_REG_BSSID_FILTER_HIGH_ADDR); 127 } 128 129 static inline void XPU_REG_BAND_CHANNEL_write(u32 Data) { 130 reg_write(XPU_REG_BAND_CHANNEL_ADDR, Data); 131 } 132 133 static inline u32 XPU_REG_BAND_CHANNEL_read(void){ 134 return reg_read(XPU_REG_BAND_CHANNEL_ADDR); 135 } 136 137 static inline void XPU_REG_DIFS_ADVANCE_write(u32 Data) { 138 reg_write(XPU_REG_DIFS_ADVANCE_ADDR, Data); 139 } 140 141 static inline u32 XPU_REG_DIFS_ADVANCE_read(void){ 142 return reg_read(XPU_REG_DIFS_ADVANCE_ADDR); 143 } 144 145 static inline u32 XPU_REG_TRX_STATUS_read(void){ 146 return reg_read(XPU_REG_TRX_STATUS_ADDR); 147 } 148 149 static inline u32 XPU_REG_TX_RESULT_read(void){ 150 return reg_read(XPU_REG_TX_RESULT_ADDR); 151 } 152 153 static inline u32 XPU_REG_TSF_RUNTIME_VAL_LOW_read(void){ 154 return reg_read(XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR); 155 } 156 157 static inline u32 XPU_REG_TSF_RUNTIME_VAL_HIGH_read(void){ 158 return reg_read(XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR); 159 } 160 161 static inline void XPU_REG_TSF_LOAD_VAL_LOW_write(u32 value){ 162 reg_write(XPU_REG_TSF_LOAD_VAL_LOW_ADDR, value); 163 } 164 165 static inline void XPU_REG_TSF_LOAD_VAL_HIGH_write(u32 value){ 166 reg_write(XPU_REG_TSF_LOAD_VAL_HIGH_ADDR, value); 167 } 168 169 static inline void XPU_REG_TSF_LOAD_VAL_write(u32 high_value, u32 low_value){ 170 XPU_REG_TSF_LOAD_VAL_LOW_write(low_value); 171 XPU_REG_TSF_LOAD_VAL_HIGH_write(high_value|0x80000000); // msb high 172 XPU_REG_TSF_LOAD_VAL_HIGH_write(high_value&(~0x80000000)); // msb low 173 } 174 175 static inline u32 XPU_REG_FC_DI_read(void){ 176 return reg_read(XPU_REG_FC_DI_ADDR); 177 } 178 179 static inline u32 XPU_REG_ADDR1_LOW_read(void){ 180 return reg_read(XPU_REG_ADDR1_LOW_ADDR); 181 } 182 183 static inline u32 XPU_REG_ADDR1_HIGH_read(void){ 184 return reg_read(XPU_REG_ADDR1_HIGH_ADDR); 185 } 186 187 static inline u32 XPU_REG_ADDR2_LOW_read(void){ 188 return reg_read(XPU_REG_ADDR2_LOW_ADDR); 189 } 190 191 static inline u32 XPU_REG_ADDR2_HIGH_read(void){ 192 return reg_read(XPU_REG_ADDR2_HIGH_ADDR); 193 } 194 195 // static inline void XPU_REG_LBT_TH_write(u32 value, u32 en_flag) { 196 // if (en_flag) { 197 // reg_write(XPU_REG_LBT_TH_ADDR, value&0x7FFFFFFF); 198 // } else { 199 // reg_write(XPU_REG_LBT_TH_ADDR, value|0x80000000); 200 // } 201 // } 202 203 static inline void XPU_REG_LBT_TH_write(u32 value) { 204 reg_write(XPU_REG_LBT_TH_ADDR, value); 205 } 206 207 static inline u32 XPU_REG_RSSI_DB_CFG_read(void){ 208 return reg_read(XPU_REG_RSSI_DB_CFG_ADDR); 209 } 210 211 static inline void XPU_REG_RSSI_DB_CFG_write(u32 Data) { 212 reg_write(XPU_REG_RSSI_DB_CFG_ADDR, Data); 213 } 214 215 static inline u32 XPU_REG_LBT_TH_read(void){ 216 return reg_read(XPU_REG_LBT_TH_ADDR); 217 } 218 219 static inline void XPU_REG_CSMA_DEBUG_write(u32 value){ 220 reg_write(XPU_REG_CSMA_DEBUG_ADDR, value); 221 } 222 223 static inline u32 XPU_REG_CSMA_DEBUG_read(void){ 224 return reg_read(XPU_REG_CSMA_DEBUG_ADDR); 225 } 226 227 static inline void XPU_REG_CSMA_CFG_write(u32 value){ 228 reg_write(XPU_REG_CSMA_CFG_ADDR, value); 229 } 230 231 static inline u32 XPU_REG_CSMA_CFG_read(void){ 232 return reg_read(XPU_REG_CSMA_CFG_ADDR); 233 } 234 235 static inline void XPU_REG_SLICE_COUNT_TOTAL_write(u32 value){ 236 reg_write(XPU_REG_SLICE_COUNT_TOTAL_ADDR, value); 237 } 238 static inline void XPU_REG_SLICE_COUNT_START_write(u32 value){ 239 reg_write(XPU_REG_SLICE_COUNT_START_ADDR, value); 240 } 241 static inline void XPU_REG_SLICE_COUNT_END_write(u32 value){ 242 reg_write(XPU_REG_SLICE_COUNT_END_ADDR, value); 243 } 244 245 246 static inline u32 XPU_REG_SLICE_COUNT_TOTAL_read(void){ 247 return reg_read(XPU_REG_SLICE_COUNT_TOTAL_ADDR); 248 } 249 static inline u32 XPU_REG_SLICE_COUNT_START_read(void){ 250 return reg_read(XPU_REG_SLICE_COUNT_START_ADDR); 251 } 252 static inline u32 XPU_REG_SLICE_COUNT_END_read(void){ 253 return reg_read(XPU_REG_SLICE_COUNT_END_ADDR); 254 } 255 256 257 static inline void XPU_REG_BB_RF_DELAY_write(u32 value){ 258 reg_write(XPU_REG_BB_RF_DELAY_ADDR, value); 259 } 260 261 static inline void XPU_REG_MAX_NUM_RETRANS_write(u32 value){ 262 reg_write(XPU_REG_MAX_NUM_RETRANS_ADDR, value); 263 } 264 265 static inline void XPU_REG_MAC_ADDR_write(u8 *mac_addr) {//, u32 en_flag){ 266 XPU_REG_MAC_ADDR_LOW_write( *( (u32*)(mac_addr) ) ); 267 XPU_REG_MAC_ADDR_HIGH_write( *( (u16*)(mac_addr + 4) ) ); 268 #if 0 269 if (en_flag) { 270 XPU_REG_MAC_ADDR_HIGH_write( (*( (u16*)(mac_addr + 4) )) | 0x80000000 ); // 0x80000000 by default we turn on mac addr filter 271 } else { 272 XPU_REG_MAC_ADDR_HIGH_write( (*( (u16*)(mac_addr + 4) )) & 0x7FFFFFFF ); 273 } 274 #endif 275 } 276 277 static const struct of_device_id dev_of_ids[] = { 278 { .compatible = "sdr,xpu", }, 279 {} 280 }; 281 MODULE_DEVICE_TABLE(of, dev_of_ids); 282 283 static struct xpu_driver_api xpu_driver_api_inst; 284 static struct xpu_driver_api *xpu_api = &xpu_driver_api_inst; 285 EXPORT_SYMBOL(xpu_api); 286 287 static inline u32 hw_init(enum xpu_mode mode){ 288 int err=0, i, rssi_half_db_th, rssi_half_db_offset, agc_gain_delay; 289 u32 filter_flag = 0, reg_val; 290 291 printk("%s hw_init mode %d\n", xpu_compatible_str, mode); 292 293 //rst 294 for (i=0;i<8;i++) 295 xpu_api->XPU_REG_MULTI_RST_write(0); 296 for (i=0;i<32;i++) 297 xpu_api->XPU_REG_MULTI_RST_write(0xFFFFFFFF); 298 for (i=0;i<8;i++) 299 xpu_api->XPU_REG_MULTI_RST_write(0); 300 301 // http://www.studioreti.it/slide/802-11-Frame_E_C.pdf 302 // https://mrncciew.com/2014/10/14/cwap-802-11-phy-ppdu/ 303 // https://mrncciew.com/2014/09/27/cwap-mac-header-frame-control/ 304 // https://mrncciew.com/2014/10/25/cwap-mac-header-durationid/ 305 // https://mrncciew.com/2014/11/01/cwap-mac-header-sequence-control/ 306 // https://witestlab.poly.edu/blog/802-11-wireless-lan-2/ 307 // phy_rx byte idx: 308 // 5(3 sig + 2 service), -- PHY 309 // 2 frame control, 2 duration/conn ID, --MAC PDU 310 // 6 receiver address, 6 destination address, 6 transmitter address 311 // 2 sequence control 312 // 6 source address 313 // reg_val = 5 + 0; 314 // xpu_api->XPU_REG_PHY_RX_PKT_READ_OFFSET_write(reg_val); 315 // printk("%s hw_init XPU_REG_PHY_RX_PKT_READ_OFFSET_write %d\n", xpu_compatible_str, reg_val); 316 317 // by default turn off filter, because all register are zeros 318 // let's filter out packet according to: enum ieee80211_filter_flags at: https://www.kernel.org/doc/html/v4.9/80211/mac80211.html 319 #if 0 // define in FPGA 320 localparam [13:0] FIF_ALLMULTI = 14b00000000000010, //get all mac addr like 01:00:5E:xx:xx:xx and 33:33:xx:xx:xx:xx through to ARM 321 FIF_FCSFAIL = 14b00000000000100, //not support 322 FIF_PLCPFAIL = 14b00000000001000, //not support 323 FIF_BCN_PRBRESP_PROMISC= 14b00000000010000, 324 FIF_CONTROL = 14b00000000100000, 325 FIF_OTHER_BSS = 14b00000001000000, 326 FIF_PSPOLL = 14b00000010000000, 327 FIF_PROBE_REQ = 14b00000100000000, 328 UNICAST_FOR_US = 14b00001000000000, 329 BROADCAST_ALL_ONE = 14b00010000000000, 330 BROADCAST_ALL_ZERO = 14b00100000000000, 331 MY_BEACON = 14b01000000000000, 332 MONITOR_ALL = 14b10000000000000; 333 #endif 334 filter_flag = (FIF_ALLMULTI|FIF_FCSFAIL|FIF_PLCPFAIL|FIF_BCN_PRBRESP_PROMISC|FIF_CONTROL|FIF_OTHER_BSS|FIF_PSPOLL|FIF_PROBE_REQ|UNICAST_FOR_US|BROADCAST_ALL_ONE|BROADCAST_ALL_ZERO|MY_BEACON|MONITOR_ALL); 335 xpu_api->XPU_REG_FILTER_FLAG_write(filter_flag); 336 xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_write(0xB<<16);//6M 1011:0xB 337 338 // after send data frame wait for ACK, this will be set in real time in function ad9361_rf_set_channel 339 // xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2)*10)<<16) | 10 ); // high 16 bits to cover sig valid of ACK packet, low 16 bits is adjustment of fcs valid waiting time. let's add 2us for those device that is really "slow"! 340 // xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( 6*10 ); // +6 = 16us for 5GHz 341 342 //xpu_api->XPU_REG_MAX_NUM_RETRANS_write(3); // if this > 0, it will override mac80211 set value, and set static retransmission limit 343 344 // xpu_api->XPU_REG_BB_RF_DELAY_write((1<<8)|47); 345 xpu_api->XPU_REG_BB_RF_DELAY_write((10<<8)|40); // extended rf is ongoing for perfect muting. (10<<8)|40 is verified good for zcu102/zed 346 347 // setup time schedule of 4 slices 348 // slice 0 349 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write(50000-1); // total 50ms 350 xpu_api->XPU_REG_SLICE_COUNT_START_write(0); //start 0ms 351 xpu_api->XPU_REG_SLICE_COUNT_END_write(50000-1); //end 50ms 352 353 // slice 1 354 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((1<<20)|(50000-1)); // total 50ms 355 xpu_api->XPU_REG_SLICE_COUNT_START_write((1<<20)|(0)); //start 0ms 356 //xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(20000-1)); //end 20ms 357 xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(50000-1)); //end 20ms 358 359 // slice 2 360 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((2<<20)|(50000-1)); // total 50ms 361 //xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(20000)); //start 20ms 362 xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(0)); //start 20ms 363 //xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(40000-1)); //end 20ms 364 xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(50000-1)); //end 20ms 365 366 // slice 3 367 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((3<<20)|(50000-1)); // total 50ms 368 //xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(40000)); //start 40ms 369 xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(0)); //start 40ms 370 //xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms 371 xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms 372 373 // all slice sync rest 374 xpu_api->XPU_REG_MULTI_RST_write(1<<7); //bit7 reset the counter for all queues at the same time 375 xpu_api->XPU_REG_MULTI_RST_write(0<<7); 376 377 switch(mode) 378 { 379 case XPU_TEST: 380 printk("%s hw_init mode XPU_TEST\n", xpu_compatible_str); 381 break; 382 383 case XPU_NORMAL: 384 printk("%s hw_init mode XPU_NORMAL\n", xpu_compatible_str); 385 break; 386 387 default: 388 printk("%s hw_init mode %d is wrong!\n", xpu_compatible_str, mode); 389 err=1; 390 } 391 xpu_api->XPU_REG_BAND_CHANNEL_write((false<<24)|(BAND_5_8GHZ<<16)|44);//use_short_slot==false; 5.8GHz; channel 44 -- default setting to sync with priv->band/channel/use_short_slot 392 393 agc_gain_delay = 50; //samples 394 rssi_half_db_offset = 75<<1; 395 xpu_api->XPU_REG_RSSI_DB_CFG_write(0x80000000|((rssi_half_db_offset<<16)|agc_gain_delay) ); 396 xpu_api->XPU_REG_RSSI_DB_CFG_write((~0x80000000)&((rssi_half_db_offset<<16)|agc_gain_delay) ); 397 398 //rssi_half_db_th = 70<<1; // with splitter 399 rssi_half_db_th = 87<<1; // -62dBm 400 reg_val=xpu_api->XPU_REG_LBT_TH_read(); 401 xpu_api->XPU_REG_LBT_TH_write((reg_val & 0xFFFF0000) | rssi_half_db_th); // set IQ rssi th step .5dB to xxx and enable it 402 403 //xpu_api->XPU_REG_CSMA_DEBUG_write((1<<31)|(20<<24)|(4<<19)|(3<<14)|(10<<7)|(5)); 404 xpu_api->XPU_REG_CSMA_DEBUG_write(0); 405 406 xpu_api->XPU_REG_CSMA_CFG_write(268435459); // 0x10000003, min CSMA cw exp = 3, set bit 28 high for dynamic CW 407 // xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); //high priority 408 409 xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((51)<<16)|0 );//now our tx send out I/Q immediately 410 411 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) 412 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) 413 414 xpu_api->XPU_REG_DIFS_ADVANCE_write(2); //us 415 416 printk("%s hw_init err %d\n", xpu_compatible_str, err); 417 return(err); 418 } 419 420 static int dev_probe(struct platform_device *pdev) 421 { 422 struct device_node *np = pdev->dev.of_node; 423 struct resource *io; 424 u32 test_us0, test_us1, test_us2; 425 int err=1; 426 427 printk("\n"); 428 429 if (np) { 430 const struct of_device_id *match; 431 432 match = of_match_node(dev_of_ids, np); 433 if (match) { 434 printk("%s dev_probe match!\n", xpu_compatible_str); 435 err = 0; 436 } 437 } 438 439 if (err) 440 return err; 441 442 xpu_api->hw_init=hw_init; 443 444 xpu_api->reg_read=reg_read; 445 xpu_api->reg_write=reg_write; 446 447 xpu_api->XPU_REG_MULTI_RST_write=XPU_REG_MULTI_RST_write; 448 xpu_api->XPU_REG_MULTI_RST_read=XPU_REG_MULTI_RST_read; 449 xpu_api->XPU_REG_SRC_SEL_write=XPU_REG_SRC_SEL_write; 450 xpu_api->XPU_REG_SRC_SEL_read=XPU_REG_SRC_SEL_read; 451 452 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write=XPU_REG_RECV_ACK_COUNT_TOP0_write; 453 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_read=XPU_REG_RECV_ACK_COUNT_TOP0_read; 454 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write=XPU_REG_RECV_ACK_COUNT_TOP1_write; 455 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_read=XPU_REG_RECV_ACK_COUNT_TOP1_read; 456 xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write=XPU_REG_SEND_ACK_WAIT_TOP_write; 457 xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_read=XPU_REG_SEND_ACK_WAIT_TOP_read; 458 xpu_api->XPU_REG_MAC_ADDR_LOW_write=XPU_REG_MAC_ADDR_LOW_write; 459 xpu_api->XPU_REG_MAC_ADDR_LOW_read=XPU_REG_MAC_ADDR_LOW_read; 460 xpu_api->XPU_REG_MAC_ADDR_HIGH_write=XPU_REG_MAC_ADDR_HIGH_write; 461 xpu_api->XPU_REG_MAC_ADDR_HIGH_read=XPU_REG_MAC_ADDR_HIGH_read; 462 463 xpu_api->XPU_REG_FILTER_FLAG_write=XPU_REG_FILTER_FLAG_write; 464 xpu_api->XPU_REG_FILTER_FLAG_read=XPU_REG_FILTER_FLAG_read; 465 xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_write=XPU_REG_CTS_TO_RTS_CONFIG_write; 466 xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_read=XPU_REG_CTS_TO_RTS_CONFIG_read; 467 xpu_api->XPU_REG_BSSID_FILTER_LOW_write=XPU_REG_BSSID_FILTER_LOW_write; 468 xpu_api->XPU_REG_BSSID_FILTER_LOW_read=XPU_REG_BSSID_FILTER_LOW_read; 469 xpu_api->XPU_REG_BSSID_FILTER_HIGH_write=XPU_REG_BSSID_FILTER_HIGH_write; 470 xpu_api->XPU_REG_BSSID_FILTER_HIGH_read=XPU_REG_BSSID_FILTER_HIGH_read; 471 472 xpu_api->XPU_REG_BAND_CHANNEL_write=XPU_REG_BAND_CHANNEL_write; 473 xpu_api->XPU_REG_BAND_CHANNEL_read=XPU_REG_BAND_CHANNEL_read; 474 475 xpu_api->XPU_REG_DIFS_ADVANCE_write=XPU_REG_DIFS_ADVANCE_write; 476 xpu_api->XPU_REG_DIFS_ADVANCE_read=XPU_REG_DIFS_ADVANCE_read; 477 478 xpu_api->XPU_REG_TRX_STATUS_read=XPU_REG_TRX_STATUS_read; 479 xpu_api->XPU_REG_TX_RESULT_read=XPU_REG_TX_RESULT_read; 480 481 xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read=XPU_REG_TSF_RUNTIME_VAL_LOW_read; 482 xpu_api->XPU_REG_TSF_RUNTIME_VAL_HIGH_read=XPU_REG_TSF_RUNTIME_VAL_HIGH_read; 483 xpu_api->XPU_REG_TSF_LOAD_VAL_LOW_write=XPU_REG_TSF_LOAD_VAL_LOW_write; 484 xpu_api->XPU_REG_TSF_LOAD_VAL_HIGH_write=XPU_REG_TSF_LOAD_VAL_HIGH_write; 485 xpu_api->XPU_REG_TSF_LOAD_VAL_write=XPU_REG_TSF_LOAD_VAL_write; 486 487 xpu_api->XPU_REG_FC_DI_read=XPU_REG_FC_DI_read; 488 xpu_api->XPU_REG_ADDR1_LOW_read=XPU_REG_ADDR1_LOW_read; 489 xpu_api->XPU_REG_ADDR1_HIGH_read=XPU_REG_ADDR1_HIGH_read; 490 xpu_api->XPU_REG_ADDR2_LOW_read=XPU_REG_ADDR2_LOW_read; 491 xpu_api->XPU_REG_ADDR2_HIGH_read=XPU_REG_ADDR2_HIGH_read; 492 493 xpu_api->XPU_REG_LBT_TH_write=XPU_REG_LBT_TH_write; 494 xpu_api->XPU_REG_LBT_TH_read=XPU_REG_LBT_TH_read; 495 496 xpu_api->XPU_REG_RSSI_DB_CFG_read=XPU_REG_RSSI_DB_CFG_read; 497 xpu_api->XPU_REG_RSSI_DB_CFG_write=XPU_REG_RSSI_DB_CFG_write; 498 499 xpu_api->XPU_REG_CSMA_DEBUG_write=XPU_REG_CSMA_DEBUG_write; 500 xpu_api->XPU_REG_CSMA_DEBUG_read=XPU_REG_CSMA_DEBUG_read; 501 502 xpu_api->XPU_REG_CSMA_CFG_write=XPU_REG_CSMA_CFG_write; 503 xpu_api->XPU_REG_CSMA_CFG_read=XPU_REG_CSMA_CFG_read; 504 505 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write=XPU_REG_SLICE_COUNT_TOTAL_write; 506 xpu_api->XPU_REG_SLICE_COUNT_START_write=XPU_REG_SLICE_COUNT_START_write; 507 xpu_api->XPU_REG_SLICE_COUNT_END_write=XPU_REG_SLICE_COUNT_END_write; 508 509 xpu_api->XPU_REG_SLICE_COUNT_TOTAL_read=XPU_REG_SLICE_COUNT_TOTAL_read; 510 xpu_api->XPU_REG_SLICE_COUNT_START_read=XPU_REG_SLICE_COUNT_START_read; 511 xpu_api->XPU_REG_SLICE_COUNT_END_read=XPU_REG_SLICE_COUNT_END_read; 512 513 xpu_api->XPU_REG_BB_RF_DELAY_write=XPU_REG_BB_RF_DELAY_write; 514 xpu_api->XPU_REG_MAX_NUM_RETRANS_write=XPU_REG_MAX_NUM_RETRANS_write; 515 516 xpu_api->XPU_REG_MAC_ADDR_write=XPU_REG_MAC_ADDR_write; 517 518 /* Request and map I/O memory */ 519 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 520 base_addr = devm_ioremap_resource(&pdev->dev, io); 521 if (IS_ERR(base_addr)) 522 return PTR_ERR(base_addr); 523 524 printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", xpu_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); 525 printk("%s dev_probe base_addr 0x%08x\n", xpu_compatible_str,(u32)base_addr); 526 printk("%s dev_probe xpu_driver_api_inst 0x%08x\n", xpu_compatible_str, (u32)&xpu_driver_api_inst); 527 printk("%s dev_probe xpu_api 0x%08x\n", xpu_compatible_str, (u32)xpu_api); 528 529 printk("%s dev_probe reset tsf timer\n", xpu_compatible_str); 530 xpu_api->XPU_REG_TSF_LOAD_VAL_write(0,0); 531 test_us0 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read(); 532 mdelay(33); 533 test_us1 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read(); 534 mdelay(67); 535 test_us2 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read(); 536 printk("%s dev_probe XPU_REG_TSF_RUNTIME_VAL_LOW_read %d %d %dus\n", xpu_compatible_str, test_us0, test_us1, test_us2); 537 538 printk("%s dev_probe succeed!\n", xpu_compatible_str); 539 540 err = hw_init(XPU_NORMAL); 541 542 return err; 543 } 544 545 static int dev_remove(struct platform_device *pdev) 546 { 547 printk("\n"); 548 549 printk("%s dev_remove base_addr 0x%08x\n", xpu_compatible_str,(u32)base_addr); 550 printk("%s dev_remove xpu_driver_api_inst 0x%08x\n", xpu_compatible_str, (u32)&xpu_driver_api_inst); 551 printk("%s dev_remove xpu_api 0x%08x\n", xpu_compatible_str, (u32)xpu_api); 552 553 printk("%s dev_remove succeed!\n", xpu_compatible_str); 554 return 0; 555 } 556 557 static struct platform_driver dev_driver = { 558 .driver = { 559 .name = "sdr,xpu", 560 .owner = THIS_MODULE, 561 .of_match_table = dev_of_ids, 562 }, 563 .probe = dev_probe, 564 .remove = dev_remove, 565 }; 566 567 module_platform_driver(dev_driver); 568 569 MODULE_AUTHOR("Xianjun Jiao"); 570 MODULE_DESCRIPTION("sdr,xpu"); 571 MODULE_LICENSE("GPL v2"); 572