1 /* 2 * axi lite register access driver 3 * Xianjun jiao. [email protected]; [email protected] 4 */ 5 6 #include <linux/bitops.h> 7 #include <linux/dmapool.h> 8 #include <linux/dma/xilinx_dma.h> 9 #include <linux/init.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/module.h> 14 #include <linux/of_address.h> 15 #include <linux/of_dma.h> 16 #include <linux/of_platform.h> 17 #include <linux/of_irq.h> 18 #include <linux/slab.h> 19 #include <linux/clk.h> 20 #include <linux/io-64-nonatomic-lo-hi.h> 21 #include <linux/delay.h> 22 #include <net/mac80211.h> 23 24 #include "../hw_def.h" 25 26 static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design 27 28 /* IO accessors */ 29 static inline u32 reg_read(u32 reg) 30 { 31 return ioread32(base_addr + reg); 32 } 33 34 static inline void reg_write(u32 reg, u32 value) 35 { 36 iowrite32(value, base_addr + reg); 37 } 38 39 static inline void XPU_REG_MULTI_RST_write(u32 Data) { 40 reg_write(XPU_REG_MULTI_RST_ADDR, Data); 41 } 42 43 static inline u32 XPU_REG_MULTI_RST_read(void){ 44 return reg_read(XPU_REG_MULTI_RST_ADDR); 45 } 46 47 static inline void XPU_REG_SRC_SEL_write(u32 Data) { 48 reg_write(XPU_REG_SRC_SEL_ADDR, Data); 49 } 50 51 static inline u32 XPU_REG_SRC_SEL_read(void){ 52 return reg_read(XPU_REG_SRC_SEL_ADDR); 53 } 54 55 static inline void XPU_REG_RECV_ACK_COUNT_TOP0_write(u32 Data) { 56 reg_write(XPU_REG_RECV_ACK_COUNT_TOP0_ADDR, Data); 57 } 58 59 static inline u32 XPU_REG_RECV_ACK_COUNT_TOP0_read(void){ 60 return reg_read(XPU_REG_RECV_ACK_COUNT_TOP0_ADDR); 61 } 62 63 static inline void XPU_REG_RECV_ACK_COUNT_TOP1_write(u32 Data) { 64 reg_write(XPU_REG_RECV_ACK_COUNT_TOP1_ADDR, Data); 65 } 66 67 static inline u32 XPU_REG_RECV_ACK_COUNT_TOP1_read(void){ 68 return reg_read(XPU_REG_RECV_ACK_COUNT_TOP1_ADDR); 69 } 70 71 static inline void XPU_REG_SEND_ACK_WAIT_TOP_write(u32 Data) { 72 reg_write(XPU_REG_SEND_ACK_WAIT_TOP_ADDR, Data); 73 } 74 75 static inline u32 XPU_REG_SEND_ACK_WAIT_TOP_read(void){ 76 return reg_read(XPU_REG_SEND_ACK_WAIT_TOP_ADDR); 77 } 78 79 static inline void XPU_REG_FILTER_FLAG_write(u32 Data) { 80 reg_write(XPU_REG_FILTER_FLAG_ADDR, Data); 81 } 82 83 static inline u32 XPU_REG_FILTER_FLAG_read(void){ 84 return reg_read(XPU_REG_FILTER_FLAG_ADDR); 85 } 86 87 static inline void XPU_REG_CTS_TO_RTS_CONFIG_write(u32 Data) { 88 reg_write(XPU_REG_CTS_TO_RTS_CONFIG_ADDR, Data); 89 } 90 91 static inline u32 XPU_REG_CTS_TO_RTS_CONFIG_read(void){ 92 return reg_read(XPU_REG_CTS_TO_RTS_CONFIG_ADDR); 93 } 94 95 static inline void XPU_REG_MAC_ADDR_LOW_write(u32 Data) { 96 reg_write(XPU_REG_MAC_ADDR_LOW_ADDR, Data); 97 } 98 99 static inline u32 XPU_REG_MAC_ADDR_LOW_read(void){ 100 return reg_read(XPU_REG_MAC_ADDR_LOW_ADDR); 101 } 102 103 static inline void XPU_REG_MAC_ADDR_HIGH_write(u32 Data) { 104 reg_write(XPU_REG_MAC_ADDR_HIGH_ADDR, Data); 105 } 106 107 static inline u32 XPU_REG_MAC_ADDR_HIGH_read(void){ 108 return reg_read(XPU_REG_MAC_ADDR_HIGH_ADDR); 109 } 110 111 static inline void XPU_REG_BSSID_FILTER_LOW_write(u32 Data) { 112 reg_write(XPU_REG_BSSID_FILTER_LOW_ADDR, Data); 113 } 114 115 static inline u32 XPU_REG_BSSID_FILTER_LOW_read(void){ 116 return reg_read(XPU_REG_BSSID_FILTER_LOW_ADDR); 117 } 118 119 static inline void XPU_REG_BSSID_FILTER_HIGH_write(u32 Data) { 120 reg_write(XPU_REG_BSSID_FILTER_HIGH_ADDR, Data); 121 } 122 123 static inline u32 XPU_REG_BSSID_FILTER_HIGH_read(void){ 124 return reg_read(XPU_REG_BSSID_FILTER_HIGH_ADDR); 125 } 126 127 static inline void XPU_REG_BAND_CHANNEL_write(u32 Data) { 128 reg_write(XPU_REG_BAND_CHANNEL_ADDR, Data); 129 } 130 131 static inline u32 XPU_REG_BAND_CHANNEL_read(void){ 132 return reg_read(XPU_REG_BAND_CHANNEL_ADDR); 133 } 134 135 static inline u32 XPU_REG_TRX_STATUS_read(void){ 136 return reg_read(XPU_REG_TRX_STATUS_ADDR); 137 } 138 139 static inline u32 XPU_REG_TX_RESULT_read(void){ 140 return reg_read(XPU_REG_TX_RESULT_ADDR); 141 } 142 143 static inline u32 XPU_REG_TSF_RUNTIME_VAL_LOW_read(void){ 144 return reg_read(XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR); 145 } 146 147 static inline u32 XPU_REG_TSF_RUNTIME_VAL_HIGH_read(void){ 148 return reg_read(XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR); 149 } 150 151 static inline void XPU_REG_TSF_LOAD_VAL_LOW_write(u32 value){ 152 reg_write(XPU_REG_TSF_LOAD_VAL_LOW_ADDR, value); 153 } 154 155 static inline void XPU_REG_TSF_LOAD_VAL_HIGH_write(u32 value){ 156 reg_write(XPU_REG_TSF_LOAD_VAL_HIGH_ADDR, value); 157 } 158 159 static inline void XPU_REG_TSF_LOAD_VAL_write(u32 high_value, u32 low_value){ 160 XPU_REG_TSF_LOAD_VAL_LOW_write(low_value); 161 XPU_REG_TSF_LOAD_VAL_HIGH_write(high_value|0x80000000); // msb high 162 XPU_REG_TSF_LOAD_VAL_HIGH_write(high_value&(~0x80000000)); // msb low 163 } 164 165 static inline u32 XPU_REG_FC_DI_read(void){ 166 return reg_read(XPU_REG_FC_DI_ADDR); 167 } 168 169 static inline u32 XPU_REG_ADDR1_LOW_read(void){ 170 return reg_read(XPU_REG_ADDR1_LOW_ADDR); 171 } 172 173 static inline u32 XPU_REG_ADDR1_HIGH_read(void){ 174 return reg_read(XPU_REG_ADDR1_HIGH_ADDR); 175 } 176 177 static inline u32 XPU_REG_ADDR2_LOW_read(void){ 178 return reg_read(XPU_REG_ADDR2_LOW_ADDR); 179 } 180 181 static inline u32 XPU_REG_ADDR2_HIGH_read(void){ 182 return reg_read(XPU_REG_ADDR2_HIGH_ADDR); 183 } 184 185 // static inline void XPU_REG_LBT_TH_write(u32 value, u32 en_flag) { 186 // if (en_flag) { 187 // reg_write(XPU_REG_LBT_TH_ADDR, value&0x7FFFFFFF); 188 // } else { 189 // reg_write(XPU_REG_LBT_TH_ADDR, value|0x80000000); 190 // } 191 // } 192 193 static inline void XPU_REG_LBT_TH_write(u32 value) { 194 reg_write(XPU_REG_LBT_TH_ADDR, value); 195 } 196 197 static inline u32 XPU_REG_RSSI_DB_CFG_read(void){ 198 return reg_read(XPU_REG_RSSI_DB_CFG_ADDR); 199 } 200 201 static inline void XPU_REG_RSSI_DB_CFG_write(u32 Data) { 202 reg_write(XPU_REG_RSSI_DB_CFG_ADDR, Data); 203 } 204 205 static inline u32 XPU_REG_LBT_TH_read(void){ 206 return reg_read(XPU_REG_LBT_TH_ADDR); 207 } 208 209 static inline void XPU_REG_CSMA_DEBUG_write(u32 value){ 210 reg_write(XPU_REG_CSMA_DEBUG_ADDR, value); 211 } 212 213 static inline u32 XPU_REG_CSMA_DEBUG_read(void){ 214 return reg_read(XPU_REG_CSMA_DEBUG_ADDR); 215 } 216 217 static inline void XPU_REG_CSMA_CFG_write(u32 value){ 218 reg_write(XPU_REG_CSMA_CFG_ADDR, value); 219 } 220 221 static inline u32 XPU_REG_CSMA_CFG_read(void){ 222 return reg_read(XPU_REG_CSMA_CFG_ADDR); 223 } 224 225 static inline void XPU_REG_SLICE_COUNT_TOTAL0_write(u32 value){ 226 reg_write(XPU_REG_SLICE_COUNT_TOTAL0_ADDR, value); 227 } 228 static inline void XPU_REG_SLICE_COUNT_START0_write(u32 value){ 229 reg_write(XPU_REG_SLICE_COUNT_START0_ADDR, value); 230 } 231 static inline void XPU_REG_SLICE_COUNT_END0_write(u32 value){ 232 reg_write(XPU_REG_SLICE_COUNT_END0_ADDR, value); 233 } 234 static inline void XPU_REG_SLICE_COUNT_TOTAL1_write(u32 value){ 235 reg_write(XPU_REG_SLICE_COUNT_TOTAL1_ADDR, value); 236 } 237 static inline void XPU_REG_SLICE_COUNT_START1_write(u32 value){ 238 reg_write(XPU_REG_SLICE_COUNT_START1_ADDR, value); 239 } 240 static inline void XPU_REG_SLICE_COUNT_END1_write(u32 value){ 241 reg_write(XPU_REG_SLICE_COUNT_END1_ADDR, value); 242 } 243 244 static inline u32 XPU_REG_SLICE_COUNT_TOTAL0_read(void){ 245 return reg_read(XPU_REG_SLICE_COUNT_TOTAL0_ADDR); 246 } 247 static inline u32 XPU_REG_SLICE_COUNT_START0_read(void){ 248 return reg_read(XPU_REG_SLICE_COUNT_START0_ADDR); 249 } 250 static inline u32 XPU_REG_SLICE_COUNT_END0_read(void){ 251 return reg_read(XPU_REG_SLICE_COUNT_END0_ADDR); 252 } 253 static inline u32 XPU_REG_SLICE_COUNT_TOTAL1_read(void){ 254 return reg_read(XPU_REG_SLICE_COUNT_TOTAL1_ADDR); 255 } 256 static inline u32 XPU_REG_SLICE_COUNT_START1_read(void){ 257 return reg_read(XPU_REG_SLICE_COUNT_START1_ADDR); 258 } 259 static inline u32 XPU_REG_SLICE_COUNT_END1_read(void){ 260 return reg_read(XPU_REG_SLICE_COUNT_END1_ADDR); 261 } 262 263 static inline void XPU_REG_BB_RF_DELAY_write(u32 value){ 264 reg_write(XPU_REG_BB_RF_DELAY_ADDR, value); 265 } 266 267 static inline void XPU_REG_MAX_NUM_RETRANS_write(u32 value){ 268 reg_write(XPU_REG_MAX_NUM_RETRANS_ADDR, value); 269 } 270 271 static inline void XPU_REG_MAC_ADDR_write(u8 *mac_addr) {//, u32 en_flag){ 272 XPU_REG_MAC_ADDR_LOW_write( *( (u32*)(mac_addr) ) ); 273 XPU_REG_MAC_ADDR_HIGH_write( *( (u16*)(mac_addr + 4) ) ); 274 #if 0 275 if (en_flag) { 276 XPU_REG_MAC_ADDR_HIGH_write( (*( (u16*)(mac_addr + 4) )) | 0x80000000 ); // 0x80000000 by default we turn on mac addr filter 277 } else { 278 XPU_REG_MAC_ADDR_HIGH_write( (*( (u16*)(mac_addr + 4) )) & 0x7FFFFFFF ); 279 } 280 #endif 281 } 282 283 static const struct of_device_id dev_of_ids[] = { 284 { .compatible = "sdr,xpu", }, 285 {} 286 }; 287 MODULE_DEVICE_TABLE(of, dev_of_ids); 288 289 static struct xpu_driver_api xpu_driver_api_inst; 290 static struct xpu_driver_api *xpu_api = &xpu_driver_api_inst; 291 EXPORT_SYMBOL(xpu_api); 292 293 static inline u32 hw_init(enum xpu_mode mode){ 294 int err=0, rssi_half_db_th, rssi_half_db_offset, agc_gain_delay; 295 u32 reg_val; 296 u32 filter_flag = 0; 297 298 printk("%s hw_init mode %d\n", xpu_compatible_str, mode); 299 300 //rst internal module 301 for (reg_val=0;reg_val<32;reg_val++) 302 xpu_api->XPU_REG_MULTI_RST_write(0xFFFFFFFF); 303 xpu_api->XPU_REG_MULTI_RST_write(0); 304 305 // http://www.studioreti.it/slide/802-11-Frame_E_C.pdf 306 // https://mrncciew.com/2014/10/14/cwap-802-11-phy-ppdu/ 307 // https://mrncciew.com/2014/09/27/cwap-mac-header-frame-control/ 308 // https://mrncciew.com/2014/10/25/cwap-mac-header-durationid/ 309 // https://mrncciew.com/2014/11/01/cwap-mac-header-sequence-control/ 310 // https://witestlab.poly.edu/blog/802-11-wireless-lan-2/ 311 // phy_rx byte idx: 312 // 5(3 sig + 2 service), -- PHY 313 // 2 frame control, 2 duration/conn ID, --MAC PDU 314 // 6 receiver address, 6 destination address, 6 transmitter address 315 // 2 sequence control 316 // 6 source address 317 // reg_val = 5 + 0; 318 // xpu_api->XPU_REG_PHY_RX_PKT_READ_OFFSET_write(reg_val); 319 // printk("%s hw_init XPU_REG_PHY_RX_PKT_READ_OFFSET_write %d\n", xpu_compatible_str, reg_val); 320 321 // by default turn off filter, because all register are zeros 322 // let's filter out packet according to: enum ieee80211_filter_flags at: https://www.kernel.org/doc/html/v4.9/80211/mac80211.html 323 #if 0 // define in FPGA 324 localparam [13:0] FIF_ALLMULTI = 14b00000000000010, //get all mac addr like 01:00:5E:xx:xx:xx and 33:33:xx:xx:xx:xx through to ARM 325 FIF_FCSFAIL = 14b00000000000100, //not support 326 FIF_PLCPFAIL = 14b00000000001000, //not support 327 FIF_BCN_PRBRESP_PROMISC= 14b00000000010000, 328 FIF_CONTROL = 14b00000000100000, 329 FIF_OTHER_BSS = 14b00000001000000, 330 FIF_PSPOLL = 14b00000010000000, 331 FIF_PROBE_REQ = 14b00000100000000, 332 UNICAST_FOR_US = 14b00001000000000, 333 BROADCAST_ALL_ONE = 14b00010000000000, 334 BROADCAST_ALL_ZERO = 14b00100000000000, 335 MY_BEACON = 14b01000000000000, 336 MONITOR_ALL = 14b10000000000000; 337 #endif 338 filter_flag = (FIF_ALLMULTI|FIF_FCSFAIL|FIF_PLCPFAIL|FIF_BCN_PRBRESP_PROMISC|FIF_CONTROL|FIF_OTHER_BSS|FIF_PSPOLL|FIF_PROBE_REQ|UNICAST_FOR_US|BROADCAST_ALL_ONE|BROADCAST_ALL_ZERO|MY_BEACON|MONITOR_ALL); 339 xpu_api->XPU_REG_FILTER_FLAG_write(filter_flag); 340 xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_write(0xB<<16);//6M 1011:0xB 341 342 ////set up FC type filter for packet needs ACK -- no use, FPGA handle by itself 343 //xpu_api->XPU_REG_ACK_FC_FILTER_write((3<<(2+16))|(2<<2)); // low 16 bits target FC 16 bits; high 16 bits -- mask 344 345 // after send data frame wait for ACK, this will be set in real time in function ad9361_rf_set_channel 346 // xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2)*10)<<16) | 10 ); // high 16 bits to cover sig valid of ACK packet, low 16 bits is adjustment of fcs valid waiting time. let's add 2us for those device that is really "slow"! 347 // xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( 6*10 ); // +6 = 16us for 5GHz 348 349 //xpu_api->XPU_REG_MAX_NUM_RETRANS_write(3); // if this > 0, it will override mac80211 set value, and set static retransmission limit 350 351 xpu_api->XPU_REG_BB_RF_DELAY_write(49); 352 353 xpu_api->XPU_REG_SLICE_COUNT_TOTAL0_write(50000-1); // total 50ms 354 xpu_api->XPU_REG_SLICE_COUNT_START0_write(0); //start 0ms 355 xpu_api->XPU_REG_SLICE_COUNT_END0_write(50000-1); //end 10ms 356 xpu_api->XPU_REG_SLICE_COUNT_TOTAL1_write(50000-1); // total 50ms 357 xpu_api->XPU_REG_SLICE_COUNT_START1_write(0000); //start 0ms 358 xpu_api->XPU_REG_SLICE_COUNT_END1_write(1000-1); //end 1ms 359 360 switch(mode) 361 { 362 case XPU_TEST: 363 printk("%s hw_init mode XPU_TEST\n", xpu_compatible_str); 364 break; 365 366 case XPU_NORMAL: 367 printk("%s hw_init mode XPU_NORMAL\n", xpu_compatible_str); 368 break; 369 370 default: 371 printk("%s hw_init mode %d is wrong!\n", xpu_compatible_str, mode); 372 err=1; 373 } 374 xpu_api->XPU_REG_BAND_CHANNEL_write((false<<24)|(BAND_5_8GHZ<<16)|44);//use_short_slot==false; 5.8GHz; channel 44 -- default setting to sync with priv->band/channel/use_short_slot 375 376 agc_gain_delay = 50; //samples 377 rssi_half_db_offset = 75<<1; 378 xpu_api->XPU_REG_RSSI_DB_CFG_write(0x80000000|((rssi_half_db_offset<<16)|agc_gain_delay) ); 379 xpu_api->XPU_REG_RSSI_DB_CFG_write((~0x80000000)&((rssi_half_db_offset<<16)|agc_gain_delay) ); 380 381 //rssi_half_db_th = 70<<1; // with splitter 382 rssi_half_db_th = 87<<1; // -62dBm 383 xpu_api->XPU_REG_LBT_TH_write(rssi_half_db_th); // set IQ rssi th step .5dB to xxx and enable it 384 385 //xpu_api->XPU_REG_CSMA_DEBUG_write((1<<31)|(20<<24)|(4<<19)|(3<<14)|(10<<7)|(5)); 386 xpu_api->XPU_REG_CSMA_DEBUG_write(0); 387 388 //xpu_api->XPU_REG_CSMA_CFG_write(3); //normal CSMA 389 xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); //high priority 390 391 // xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((40)<<16)|0 );//high 16bit 5GHz; low 16 bit 2.4GHz (Attention, current tx core has around 1.19us starting delay that makes the ack fall behind 10us SIFS in 2.4GHz! Need to improve TX in 2.4GHz!) 392 xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((51)<<16)|0 );//now our tx send out I/Q immediately 393 394 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) 395 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) 396 397 printk("%s hw_init err %d\n", xpu_compatible_str, err); 398 return(err); 399 } 400 401 static int dev_probe(struct platform_device *pdev) 402 { 403 struct device_node *np = pdev->dev.of_node; 404 struct resource *io; 405 u32 test_us0, test_us1, test_us2; 406 int err=1; 407 408 printk("\n"); 409 410 if (np) { 411 const struct of_device_id *match; 412 413 match = of_match_node(dev_of_ids, np); 414 if (match) { 415 printk("%s dev_probe match!\n", xpu_compatible_str); 416 err = 0; 417 } 418 } 419 420 if (err) 421 return err; 422 423 xpu_api->hw_init=hw_init; 424 425 xpu_api->reg_read=reg_read; 426 xpu_api->reg_write=reg_write; 427 428 xpu_api->XPU_REG_MULTI_RST_write=XPU_REG_MULTI_RST_write; 429 xpu_api->XPU_REG_MULTI_RST_read=XPU_REG_MULTI_RST_read; 430 xpu_api->XPU_REG_SRC_SEL_write=XPU_REG_SRC_SEL_write; 431 xpu_api->XPU_REG_SRC_SEL_read=XPU_REG_SRC_SEL_read; 432 433 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write=XPU_REG_RECV_ACK_COUNT_TOP0_write; 434 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_read=XPU_REG_RECV_ACK_COUNT_TOP0_read; 435 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write=XPU_REG_RECV_ACK_COUNT_TOP1_write; 436 xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_read=XPU_REG_RECV_ACK_COUNT_TOP1_read; 437 xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write=XPU_REG_SEND_ACK_WAIT_TOP_write; 438 xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_read=XPU_REG_SEND_ACK_WAIT_TOP_read; 439 xpu_api->XPU_REG_MAC_ADDR_LOW_write=XPU_REG_MAC_ADDR_LOW_write; 440 xpu_api->XPU_REG_MAC_ADDR_LOW_read=XPU_REG_MAC_ADDR_LOW_read; 441 xpu_api->XPU_REG_MAC_ADDR_HIGH_write=XPU_REG_MAC_ADDR_HIGH_write; 442 xpu_api->XPU_REG_MAC_ADDR_HIGH_read=XPU_REG_MAC_ADDR_HIGH_read; 443 444 xpu_api->XPU_REG_FILTER_FLAG_write=XPU_REG_FILTER_FLAG_write; 445 xpu_api->XPU_REG_FILTER_FLAG_read=XPU_REG_FILTER_FLAG_read; 446 xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_write=XPU_REG_CTS_TO_RTS_CONFIG_write; 447 xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_read=XPU_REG_CTS_TO_RTS_CONFIG_read; 448 xpu_api->XPU_REG_BSSID_FILTER_LOW_write=XPU_REG_BSSID_FILTER_LOW_write; 449 xpu_api->XPU_REG_BSSID_FILTER_LOW_read=XPU_REG_BSSID_FILTER_LOW_read; 450 xpu_api->XPU_REG_BSSID_FILTER_HIGH_write=XPU_REG_BSSID_FILTER_HIGH_write; 451 xpu_api->XPU_REG_BSSID_FILTER_HIGH_read=XPU_REG_BSSID_FILTER_HIGH_read; 452 453 xpu_api->XPU_REG_BAND_CHANNEL_write=XPU_REG_BAND_CHANNEL_write; 454 xpu_api->XPU_REG_BAND_CHANNEL_read=XPU_REG_BAND_CHANNEL_read; 455 456 xpu_api->XPU_REG_TRX_STATUS_read=XPU_REG_TRX_STATUS_read; 457 xpu_api->XPU_REG_TX_RESULT_read=XPU_REG_TX_RESULT_read; 458 459 xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read=XPU_REG_TSF_RUNTIME_VAL_LOW_read; 460 xpu_api->XPU_REG_TSF_RUNTIME_VAL_HIGH_read=XPU_REG_TSF_RUNTIME_VAL_HIGH_read; 461 xpu_api->XPU_REG_TSF_LOAD_VAL_LOW_write=XPU_REG_TSF_LOAD_VAL_LOW_write; 462 xpu_api->XPU_REG_TSF_LOAD_VAL_HIGH_write=XPU_REG_TSF_LOAD_VAL_HIGH_write; 463 xpu_api->XPU_REG_TSF_LOAD_VAL_write=XPU_REG_TSF_LOAD_VAL_write; 464 465 xpu_api->XPU_REG_FC_DI_read=XPU_REG_FC_DI_read; 466 xpu_api->XPU_REG_ADDR1_LOW_read=XPU_REG_ADDR1_LOW_read; 467 xpu_api->XPU_REG_ADDR1_HIGH_read=XPU_REG_ADDR1_HIGH_read; 468 xpu_api->XPU_REG_ADDR2_LOW_read=XPU_REG_ADDR2_LOW_read; 469 xpu_api->XPU_REG_ADDR2_HIGH_read=XPU_REG_ADDR2_HIGH_read; 470 471 xpu_api->XPU_REG_LBT_TH_write=XPU_REG_LBT_TH_write; 472 xpu_api->XPU_REG_LBT_TH_read=XPU_REG_LBT_TH_read; 473 474 xpu_api->XPU_REG_RSSI_DB_CFG_read=XPU_REG_RSSI_DB_CFG_read; 475 xpu_api->XPU_REG_RSSI_DB_CFG_write=XPU_REG_RSSI_DB_CFG_write; 476 477 xpu_api->XPU_REG_CSMA_DEBUG_write=XPU_REG_CSMA_DEBUG_write; 478 xpu_api->XPU_REG_CSMA_DEBUG_read=XPU_REG_CSMA_DEBUG_read; 479 480 xpu_api->XPU_REG_CSMA_CFG_write=XPU_REG_CSMA_CFG_write; 481 xpu_api->XPU_REG_CSMA_CFG_read=XPU_REG_CSMA_CFG_read; 482 483 xpu_api->XPU_REG_SLICE_COUNT_TOTAL0_write=XPU_REG_SLICE_COUNT_TOTAL0_write; 484 xpu_api->XPU_REG_SLICE_COUNT_START0_write=XPU_REG_SLICE_COUNT_START0_write; 485 xpu_api->XPU_REG_SLICE_COUNT_END0_write=XPU_REG_SLICE_COUNT_END0_write; 486 xpu_api->XPU_REG_SLICE_COUNT_TOTAL1_write=XPU_REG_SLICE_COUNT_TOTAL1_write; 487 xpu_api->XPU_REG_SLICE_COUNT_START1_write=XPU_REG_SLICE_COUNT_START1_write; 488 xpu_api->XPU_REG_SLICE_COUNT_END1_write=XPU_REG_SLICE_COUNT_END1_write; 489 490 xpu_api->XPU_REG_SLICE_COUNT_TOTAL0_read=XPU_REG_SLICE_COUNT_TOTAL0_read; 491 xpu_api->XPU_REG_SLICE_COUNT_START0_read=XPU_REG_SLICE_COUNT_START0_read; 492 xpu_api->XPU_REG_SLICE_COUNT_END0_read=XPU_REG_SLICE_COUNT_END0_read; 493 xpu_api->XPU_REG_SLICE_COUNT_TOTAL1_read=XPU_REG_SLICE_COUNT_TOTAL1_read; 494 xpu_api->XPU_REG_SLICE_COUNT_START1_read=XPU_REG_SLICE_COUNT_START1_read; 495 xpu_api->XPU_REG_SLICE_COUNT_END1_read=XPU_REG_SLICE_COUNT_END1_read; 496 497 xpu_api->XPU_REG_BB_RF_DELAY_write=XPU_REG_BB_RF_DELAY_write; 498 xpu_api->XPU_REG_MAX_NUM_RETRANS_write=XPU_REG_MAX_NUM_RETRANS_write; 499 500 xpu_api->XPU_REG_MAC_ADDR_write=XPU_REG_MAC_ADDR_write; 501 502 /* Request and map I/O memory */ 503 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 504 base_addr = devm_ioremap_resource(&pdev->dev, io); 505 if (IS_ERR(base_addr)) 506 return PTR_ERR(base_addr); 507 508 printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", xpu_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); 509 printk("%s dev_probe base_addr 0x%08x\n", xpu_compatible_str,(u32)base_addr); 510 printk("%s dev_probe xpu_driver_api_inst 0x%08x\n", xpu_compatible_str, (u32)&xpu_driver_api_inst); 511 printk("%s dev_probe xpu_api 0x%08x\n", xpu_compatible_str, (u32)xpu_api); 512 513 printk("%s dev_probe reset tsf timer\n", xpu_compatible_str); 514 xpu_api->XPU_REG_TSF_LOAD_VAL_write(0,0); 515 test_us0 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read(); 516 mdelay(33); 517 test_us1 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read(); 518 mdelay(67); 519 test_us2 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read(); 520 printk("%s dev_probe XPU_REG_TSF_RUNTIME_VAL_LOW_read %d %d %dus\n", xpu_compatible_str, test_us0, test_us1, test_us2); 521 522 printk("%s dev_probe succeed!\n", xpu_compatible_str); 523 524 err = hw_init(XPU_NORMAL); 525 526 return err; 527 } 528 529 static int dev_remove(struct platform_device *pdev) 530 { 531 printk("\n"); 532 533 printk("%s dev_remove base_addr 0x%08x\n", xpu_compatible_str,(u32)base_addr); 534 printk("%s dev_remove xpu_driver_api_inst 0x%08x\n", xpu_compatible_str, (u32)&xpu_driver_api_inst); 535 printk("%s dev_remove xpu_api 0x%08x\n", xpu_compatible_str, (u32)xpu_api); 536 537 printk("%s dev_remove succeed!\n", xpu_compatible_str); 538 return 0; 539 } 540 541 static struct platform_driver dev_driver = { 542 .driver = { 543 .name = "sdr,xpu", 544 .owner = THIS_MODULE, 545 .of_match_table = dev_of_ids, 546 }, 547 .probe = dev_probe, 548 .remove = dev_remove, 549 }; 550 551 module_platform_driver(dev_driver); 552 553 MODULE_AUTHOR("Xianjun Jiao"); 554 MODULE_DESCRIPTION("sdr,xpu"); 555 MODULE_LICENSE("GPL v2"); 556