1 /* 2 * axi lite register access driver 3 * Author: Xianjun Jiao, Michael Mehari, Wei Liu 4 * SPDX-FileCopyrightText: 2019 UGent 5 * SPDX-License-Identifier: AGPL-3.0-or-later 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/dmapool.h> 10 #include <linux/dma/xilinx_dma.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/of_dma.h> 18 #include <linux/of_platform.h> 19 #include <linux/of_irq.h> 20 #include <linux/slab.h> 21 #include <linux/clk.h> 22 #include <linux/io-64-nonatomic-lo-hi.h> 23 24 #include "../hw_def.h" 25 26 static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design 27 28 /* IO accessors */ 29 static inline u32 reg_read(u32 reg) 30 { 31 return ioread32(base_addr + reg); 32 } 33 34 static inline void reg_write(u32 reg, u32 value) 35 { 36 iowrite32(value, base_addr + reg); 37 } 38 39 static inline u32 TX_INTF_REG_MULTI_RST_read(void){ 40 return reg_read(TX_INTF_REG_MULTI_RST_ADDR); 41 } 42 43 static inline u32 TX_INTF_REG_MIXER_CFG_read(void){ 44 return reg_read(TX_INTF_REG_MIXER_CFG_ADDR); 45 } 46 47 static inline u32 TX_INTF_REG_WIFI_TX_MODE_read(void){ 48 return reg_read(TX_INTF_REG_WIFI_TX_MODE_ADDR); 49 } 50 51 static inline u32 TX_INTF_REG_IQ_SRC_SEL_read(void){ 52 return reg_read(TX_INTF_REG_IQ_SRC_SEL_ADDR); 53 } 54 55 static inline u32 TX_INTF_REG_CTS_TOSELF_CONFIG_read(void){ 56 return reg_read(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR); 57 } 58 59 static inline u32 TX_INTF_REG_START_TRANS_TO_PS_MODE_read(void){ 60 return reg_read(TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR); 61 } 62 63 static inline u32 TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read(void){ 64 return reg_read(TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR); 65 } 66 67 static inline u32 TX_INTF_REG_MISC_SEL_read(void){ 68 return reg_read(TX_INTF_REG_MISC_SEL_ADDR); 69 } 70 71 static inline u32 TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read(void){ 72 return reg_read(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR); 73 } 74 75 static inline u32 TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read(void){ 76 return reg_read(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR); 77 } 78 79 static inline u32 TX_INTF_REG_CFG_DATA_TO_ANT_read(void){ 80 return reg_read(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR); 81 } 82 83 static inline u32 TX_INTF_REG_S_AXIS_FIFO_TH_read(void){ 84 return reg_read(TX_INTF_REG_S_AXIS_FIFO_TH_ADDR); 85 } 86 87 static inline u32 TX_INTF_REG_TX_HOLD_THRESHOLD_read(void){ 88 return reg_read(TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR); 89 } 90 91 static inline u32 TX_INTF_REG_INTERRUPT_SEL_read(void){ 92 return reg_read(TX_INTF_REG_INTERRUPT_SEL_ADDR); 93 } 94 95 static inline u32 TX_INTF_REG_BB_GAIN_read(void){ 96 return reg_read(TX_INTF_REG_BB_GAIN_ADDR); 97 } 98 99 static inline u32 TX_INTF_REG_ANT_SEL_read(void){ 100 return reg_read(TX_INTF_REG_ANT_SEL_ADDR); 101 } 102 103 static inline u32 TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read(void){ 104 return reg_read(TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR); 105 } 106 107 static inline u32 TX_INTF_REG_PKT_INFO_read(void){ 108 return reg_read(TX_INTF_REG_PKT_INFO_ADDR); 109 } 110 111 static inline u32 TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read(void){ 112 return reg_read(TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_ADDR); 113 } 114 115 //-------------------------------------------------------- 116 117 static inline void TX_INTF_REG_MULTI_RST_write(u32 value){ 118 reg_write(TX_INTF_REG_MULTI_RST_ADDR, value); 119 } 120 121 static inline void TX_INTF_REG_MIXER_CFG_write(u32 value){ 122 reg_write(TX_INTF_REG_MIXER_CFG_ADDR, value); 123 } 124 125 static inline void TX_INTF_REG_WIFI_TX_MODE_write(u32 value){ 126 reg_write(TX_INTF_REG_WIFI_TX_MODE_ADDR, value); 127 } 128 129 static inline void TX_INTF_REG_IQ_SRC_SEL_write(u32 value){ 130 reg_write(TX_INTF_REG_IQ_SRC_SEL_ADDR, value); 131 } 132 133 static inline void TX_INTF_REG_CTS_TOSELF_CONFIG_write(u32 value){ 134 reg_write(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR, value); 135 } 136 137 static inline void TX_INTF_REG_START_TRANS_TO_PS_MODE_write(u32 value){ 138 reg_write(TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR, value); 139 } 140 141 static inline void TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write(u32 value){ 142 reg_write(TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR, value); 143 } 144 145 static inline void TX_INTF_REG_MISC_SEL_write(u32 value){ 146 reg_write(TX_INTF_REG_MISC_SEL_ADDR, value); 147 } 148 149 static inline void TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(u32 value){ 150 reg_write(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR, value); 151 } 152 153 static inline void TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(u32 value){ 154 reg_write(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR, value); 155 } 156 157 static inline void TX_INTF_REG_CFG_DATA_TO_ANT_write(u32 value){ 158 reg_write(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR, value); 159 } 160 161 static inline void TX_INTF_REG_S_AXIS_FIFO_TH_write(u32 value){ 162 reg_write(TX_INTF_REG_S_AXIS_FIFO_TH_ADDR, value); 163 } 164 165 static inline void TX_INTF_REG_TX_HOLD_THRESHOLD_write(u32 value){ 166 reg_write(TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR, value); 167 } 168 169 static inline void TX_INTF_REG_INTERRUPT_SEL_write(u32 value){ 170 reg_write(TX_INTF_REG_INTERRUPT_SEL_ADDR, value); 171 } 172 173 static inline void TX_INTF_REG_BB_GAIN_write(u32 value){ 174 reg_write(TX_INTF_REG_BB_GAIN_ADDR, value); 175 } 176 177 static inline void TX_INTF_REG_ANT_SEL_write(u32 value){ 178 reg_write(TX_INTF_REG_ANT_SEL_ADDR, value); 179 } 180 181 static inline void TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write(u32 value){ 182 reg_write(TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR, value); 183 } 184 185 static inline void TX_INTF_REG_PKT_INFO_write(u32 value){ 186 reg_write(TX_INTF_REG_PKT_INFO_ADDR,value); 187 } 188 189 static const struct of_device_id dev_of_ids[] = { 190 { .compatible = "sdr,tx_intf", }, 191 {} 192 }; 193 MODULE_DEVICE_TABLE(of, dev_of_ids); 194 195 static struct tx_intf_driver_api tx_intf_driver_api_inst; 196 static struct tx_intf_driver_api *tx_intf_api = &tx_intf_driver_api_inst; 197 EXPORT_SYMBOL(tx_intf_api); 198 199 static inline u32 hw_init(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type){ 200 int err=0, i; 201 u32 mixer_cfg=0, duc_input_ch_sel = 0, ant_sel=0; 202 203 printk("%s hw_init mode %d\n", tx_intf_compatible_str, mode); 204 205 //rst 206 for (i=0;i<8;i++) 207 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 208 for (i=0;i<32;i++) 209 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0xFFFFFFFF); 210 for (i=0;i<8;i++) 211 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 212 213 214 if(fpga_type == LARGE_FPGA) // LARGE FPGA: MAX_NUM_DMA_SYMBOL = 8192 215 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(8192-200); // when only 200 DMA symbol room left in fifo, stop Linux queue 216 else if(fpga_type == SMALL_FPGA) // SMALL FPGA: MAX_NUM_DMA_SYMBOL = 4096 217 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(4096-200); // when only 200 DMA symbol room left in fifo, stop Linux queue 218 219 switch(mode) 220 { 221 case TX_INTF_AXIS_LOOP_BACK: 222 tx_intf_api->TX_INTF_REG_MISC_SEL_write(0<<1);// bit1: 0-connect dac to ADI dma; 1-connect dac to our intf 223 printk("%s hw_init mode TX_INTF_AXIS_LOOP_BACK\n", tx_intf_compatible_str); 224 break; 225 226 case TX_INTF_BW_20MHZ_AT_0MHZ_ANT0: 227 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT0\n", tx_intf_compatible_str); 228 mixer_cfg = 0x2001F400; 229 duc_input_ch_sel = 0; 230 ant_sel=1; 231 break; 232 233 case TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0: 234 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0\n", tx_intf_compatible_str); 235 mixer_cfg = 0x2001F602; 236 duc_input_ch_sel = 0; 237 ant_sel=1; 238 break; 239 240 case TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0: 241 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0\n", tx_intf_compatible_str); 242 mixer_cfg = 0x200202F6; 243 duc_input_ch_sel = 0; 244 ant_sel=1; 245 break; 246 247 case TX_INTF_BW_20MHZ_AT_0MHZ_ANT1: 248 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT1\n", tx_intf_compatible_str); 249 mixer_cfg = 0x2001F400; 250 duc_input_ch_sel = 0; 251 ant_sel=2; 252 break; 253 254 case TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1: 255 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1\n", tx_intf_compatible_str); 256 mixer_cfg = 0x2001F602; 257 duc_input_ch_sel = 0; 258 ant_sel=2; 259 break; 260 261 case TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1: 262 printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1\n", tx_intf_compatible_str); 263 mixer_cfg = 0x200202F6; 264 duc_input_ch_sel = 0; 265 ant_sel=2; 266 break; 267 268 case TX_INTF_BYPASS: 269 printk("%s hw_init mode TX_INTF_BYPASS\n", tx_intf_compatible_str); 270 mixer_cfg = 0x200202F6; 271 duc_input_ch_sel = 0; 272 ant_sel=2; 273 break; 274 275 default: 276 printk("%s hw_init mode %d is wrong!\n", tx_intf_compatible_str, mode); 277 err=1; 278 } 279 280 if (mode!=TX_INTF_AXIS_LOOP_BACK) { 281 tx_intf_api->TX_INTF_REG_MISC_SEL_write(1<<1);// bit1: 0-connect dac to ADI dma; 1-connect dac to our intf 282 283 tx_intf_api->TX_INTF_REG_MIXER_CFG_write(mixer_cfg); 284 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 285 tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_write(duc_input_ch_sel); 286 tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_write(2); 287 tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*10)<<16)|(10*10) );//high 16bit 5GHz; low 16 bit 2.4GHz. counter speed 10MHz is assumed 288 289 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(num_dma_symbol_to_pl); 290 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps); 291 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0); 292 tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_write(420); 293 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x4); //.src_sel(slv_reg14[2:0]), 0-s00_axis_tlast,1-ap_start,2-tx_start_from_acc,3-tx_end_from_acc,4-tx_try_complete from xpu 294 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x30004); //disable interrupt 295 tx_intf_api->TX_INTF_REG_BB_GAIN_write(100); 296 tx_intf_api->TX_INTF_REG_ANT_SEL_write(ant_sel); 297 tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write((1<<3)|(2<<4)); 298 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0x434); 299 tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); 300 } 301 302 if (mode == TX_INTF_BYPASS) { 303 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0x100); //slv_reg10[8] 304 } 305 306 printk("%s hw_init err %d\n", tx_intf_compatible_str, err); 307 return(err); 308 } 309 310 static int dev_probe(struct platform_device *pdev) 311 { 312 struct device_node *np = pdev->dev.of_node; 313 struct resource *io; 314 int err=1; 315 316 printk("\n"); 317 318 if (np) { 319 const struct of_device_id *match; 320 321 match = of_match_node(dev_of_ids, np); 322 if (match) { 323 printk("%s dev_probe match!\n", tx_intf_compatible_str); 324 err = 0; 325 } 326 } 327 328 if (err) 329 return err; 330 331 tx_intf_api->hw_init=hw_init; 332 333 tx_intf_api->reg_read=reg_read; 334 tx_intf_api->reg_write=reg_write; 335 336 tx_intf_api->TX_INTF_REG_MULTI_RST_read=TX_INTF_REG_MULTI_RST_read; 337 tx_intf_api->TX_INTF_REG_MIXER_CFG_read=TX_INTF_REG_MIXER_CFG_read; 338 tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_read=TX_INTF_REG_WIFI_TX_MODE_read; 339 tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_read=TX_INTF_REG_IQ_SRC_SEL_read; 340 tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_read=TX_INTF_REG_CTS_TOSELF_CONFIG_read; 341 tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_read=TX_INTF_REG_START_TRANS_TO_PS_MODE_read; 342 tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read; 343 tx_intf_api->TX_INTF_REG_MISC_SEL_read=TX_INTF_REG_MISC_SEL_read; 344 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read; 345 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read; 346 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_read=TX_INTF_REG_CFG_DATA_TO_ANT_read; 347 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_read=TX_INTF_REG_S_AXIS_FIFO_TH_read; 348 tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_read=TX_INTF_REG_TX_HOLD_THRESHOLD_read; 349 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_read=TX_INTF_REG_INTERRUPT_SEL_read; 350 tx_intf_api->TX_INTF_REG_BB_GAIN_read=TX_INTF_REG_BB_GAIN_read; 351 tx_intf_api->TX_INTF_REG_ANT_SEL_read=TX_INTF_REG_ANT_SEL_read; 352 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read=TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read; 353 tx_intf_api->TX_INTF_REG_PKT_INFO_read=TX_INTF_REG_PKT_INFO_read; 354 tx_intf_api->TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read=TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read; 355 356 tx_intf_api->TX_INTF_REG_MULTI_RST_write=TX_INTF_REG_MULTI_RST_write; 357 tx_intf_api->TX_INTF_REG_MIXER_CFG_write=TX_INTF_REG_MIXER_CFG_write; 358 tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write=TX_INTF_REG_WIFI_TX_MODE_write; 359 tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_write=TX_INTF_REG_IQ_SRC_SEL_write; 360 tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_write=TX_INTF_REG_CTS_TOSELF_CONFIG_write; 361 tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_write=TX_INTF_REG_START_TRANS_TO_PS_MODE_write; 362 tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write; 363 tx_intf_api->TX_INTF_REG_MISC_SEL_write=TX_INTF_REG_MISC_SEL_write; 364 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write; 365 tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write; 366 tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write=TX_INTF_REG_CFG_DATA_TO_ANT_write; 367 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write=TX_INTF_REG_S_AXIS_FIFO_TH_write; 368 tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_write=TX_INTF_REG_TX_HOLD_THRESHOLD_write; 369 tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write=TX_INTF_REG_INTERRUPT_SEL_write; 370 tx_intf_api->TX_INTF_REG_BB_GAIN_write=TX_INTF_REG_BB_GAIN_write; 371 tx_intf_api->TX_INTF_REG_ANT_SEL_write=TX_INTF_REG_ANT_SEL_write; 372 tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write=TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write; 373 tx_intf_api->TX_INTF_REG_PKT_INFO_write=TX_INTF_REG_PKT_INFO_write; 374 375 /* Request and map I/O memory */ 376 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 377 base_addr = devm_ioremap_resource(&pdev->dev, io); 378 if (IS_ERR(base_addr)) 379 return PTR_ERR(base_addr); 380 381 printk("%s dev_probe io start 0x%08llx end 0x%08llx name %s flags 0x%08x desc 0x%08x\n", tx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); 382 printk("%s dev_probe base_addr 0x%p\n", tx_intf_compatible_str,(void*)base_addr); 383 printk("%s dev_probe tx_intf_driver_api_inst 0x%p\n", tx_intf_compatible_str, (void*)(&tx_intf_driver_api_inst) ); 384 printk("%s dev_probe tx_intf_api 0x%p\n", tx_intf_compatible_str, (void*)tx_intf_api); 385 386 printk("%s dev_probe succeed!\n", tx_intf_compatible_str); 387 388 //err = hw_init(TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 8, 8, SMALL_FPGA); 389 //err = hw_init(TX_INTF_BYPASS, 8, 8, SMALL_FPGA); 390 err = hw_init(TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 8, 8, SMALL_FPGA); // make sure dac is connected to original ad9361 dma 391 392 return err; 393 } 394 395 static int dev_remove(struct platform_device *pdev) 396 { 397 printk("\n"); 398 399 printk("%s dev_remove base_addr 0x%p\n", tx_intf_compatible_str,(void*)base_addr); 400 printk("%s dev_remove tx_intf_driver_api_inst 0x%p\n", tx_intf_compatible_str, (void*)(&tx_intf_driver_api_inst) ); 401 printk("%s dev_remove tx_intf_api 0x%p\n", tx_intf_compatible_str, (void*)tx_intf_api); 402 403 printk("%s dev_remove succeed!\n", tx_intf_compatible_str); 404 return 0; 405 } 406 407 static struct platform_driver dev_driver = { 408 .driver = { 409 .name = "sdr,tx_intf", 410 .owner = THIS_MODULE, 411 .of_match_table = dev_of_ids, 412 }, 413 .probe = dev_probe, 414 .remove = dev_remove, 415 }; 416 417 module_platform_driver(dev_driver); 418 419 MODULE_AUTHOR("Xianjun Jiao"); 420 MODULE_DESCRIPTION("sdr,tx_intf"); 421 MODULE_LICENSE("GPL v2"); 422