1 /* 2 * axi lite register access driver 3 * Xianjun jiao. [email protected]; [email protected] 4 */ 5 6 #include <linux/bitops.h> 7 #include <linux/dmapool.h> 8 #include <linux/dma/xilinx_dma.h> 9 #include <linux/init.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/module.h> 14 #include <linux/of_address.h> 15 #include <linux/of_dma.h> 16 #include <linux/of_platform.h> 17 #include <linux/of_irq.h> 18 #include <linux/slab.h> 19 #include <linux/clk.h> 20 #include <linux/io-64-nonatomic-lo-hi.h> 21 22 #include "../hw_def.h" 23 24 static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design 25 26 /* IO accessors */ 27 static inline u32 reg_read(u32 reg) 28 { 29 return ioread32(base_addr + reg); 30 } 31 32 static inline void reg_write(u32 reg, u32 value) 33 { 34 iowrite32(value, base_addr + reg); 35 } 36 37 static inline u32 RX_INTF_REG_MULTI_RST_read(void){ 38 return reg_read(RX_INTF_REG_MULTI_RST_ADDR); 39 } 40 41 static inline u32 RX_INTF_REG_MIXER_CFG_read(void){ 42 return reg_read(RX_INTF_REG_MIXER_CFG_ADDR); 43 } 44 45 static inline u32 RX_INTF_REG_IQ_SRC_SEL_read(void){ 46 return reg_read(RX_INTF_REG_IQ_SRC_SEL_ADDR); 47 } 48 49 static inline u32 RX_INTF_REG_IQ_CTRL_read(void){ 50 return reg_read(RX_INTF_REG_IQ_CTRL_ADDR); 51 } 52 53 static inline u32 RX_INTF_REG_START_TRANS_TO_PS_MODE_read(void){ 54 return reg_read(RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR); 55 } 56 57 static inline u32 RX_INTF_REG_START_TRANS_TO_PS_read(void){ 58 return reg_read(RX_INTF_REG_START_TRANS_TO_PS_ADDR); 59 } 60 61 static inline u32 RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read(void){ 62 return reg_read(RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR); 63 } 64 65 static inline u32 RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read(void){ 66 return reg_read(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR); 67 } 68 69 static inline u32 RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read(void){ 70 return reg_read(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR); 71 } 72 73 static inline u32 RX_INTF_REG_CFG_DATA_TO_ANT_read(void){ 74 return reg_read(RX_INTF_REG_CFG_DATA_TO_ANT_ADDR); 75 } 76 77 static inline u32 RX_INTF_REG_ANT_SEL_read(void){ 78 return reg_read(RX_INTF_REG_ANT_SEL_ADDR); 79 } 80 81 static inline u32 RX_INTF_REG_INTERRUPT_TEST_read(void) { 82 return reg_read(RX_INTF_REG_INTERRUPT_TEST_ADDR); 83 } 84 85 static inline void RX_INTF_REG_MULTI_RST_write(u32 value){ 86 reg_write(RX_INTF_REG_MULTI_RST_ADDR, value); 87 } 88 89 static inline void RX_INTF_REG_M_AXIS_RST_write(u32 value){ 90 u32 reg_val; 91 92 if (value==0) { 93 reg_val = RX_INTF_REG_MULTI_RST_read(); 94 reg_val = ( reg_val&(~(1<<4)) ); 95 RX_INTF_REG_MULTI_RST_write(reg_val); 96 } else { 97 reg_val = RX_INTF_REG_MULTI_RST_read(); 98 reg_val = ( reg_val|(1<<4) ); 99 RX_INTF_REG_MULTI_RST_write(reg_val); 100 } 101 } 102 103 static inline void RX_INTF_REG_MIXER_CFG_write(u32 value){ 104 reg_write(RX_INTF_REG_MIXER_CFG_ADDR, value); 105 } 106 107 static inline void RX_INTF_REG_IQ_SRC_SEL_write(u32 value){ 108 reg_write(RX_INTF_REG_IQ_SRC_SEL_ADDR, value); 109 } 110 111 static inline void RX_INTF_REG_IQ_CTRL_write(u32 value){ 112 reg_write(RX_INTF_REG_IQ_CTRL_ADDR, value); 113 } 114 115 static inline void RX_INTF_REG_START_TRANS_TO_PS_MODE_write(u32 value){ 116 reg_write(RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR, value); 117 } 118 119 static inline void RX_INTF_REG_START_TRANS_TO_PS_write(u32 value){ 120 reg_write(RX_INTF_REG_START_TRANS_TO_PS_ADDR, value); 121 } 122 123 static inline void RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write(u32 value){ 124 reg_write(RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR, value); 125 } 126 127 static inline void RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(u32 value){ 128 reg_write(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR, value); 129 } 130 131 static inline void RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(u32 value){ 132 reg_write(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR, value); 133 } 134 135 static inline void RX_INTF_REG_CFG_DATA_TO_ANT_write(u32 value){ 136 reg_write(RX_INTF_REG_CFG_DATA_TO_ANT_ADDR, value); 137 } 138 139 static inline void RX_INTF_REG_ANT_SEL_write(u32 value){ 140 reg_write(RX_INTF_REG_ANT_SEL_ADDR, value); 141 } 142 143 static inline void RX_INTF_REG_INTERRUPT_TEST_write(u32 value) { 144 reg_write(RX_INTF_REG_INTERRUPT_TEST_ADDR, value); 145 } 146 147 static inline void RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(u32 value) { 148 reg_write(RX_INTF_REG_S2MM_INTR_DELAY_COUNT_ADDR, value); 149 } 150 151 static inline void RX_INTF_REG_TLAST_TIMEOUT_TOP_write(u32 value) { 152 reg_write(RX_INTF_REG_TLAST_TIMEOUT_TOP_ADDR, value); 153 } 154 155 static const struct of_device_id dev_of_ids[] = { 156 { .compatible = "sdr,rx_intf", }, 157 {} 158 }; 159 MODULE_DEVICE_TABLE(of, dev_of_ids); 160 161 static struct rx_intf_driver_api rx_intf_driver_api_inst; 162 //EXPORT_SYMBOL(rx_intf_driver_api_inst); 163 static struct rx_intf_driver_api *rx_intf_api = &rx_intf_driver_api_inst; 164 EXPORT_SYMBOL(rx_intf_api); 165 166 static inline u32 hw_init(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps){ 167 int err=0; 168 u32 reg_val, mixer_cfg=0, ant_sel=0; 169 170 printk("%s hw_init mode %d\n", rx_intf_compatible_str, mode); 171 172 ////rst wifi rx -- slv_reg11[2] is actual rx reset. slv_reg11[0] only reset axi lite of rx 173 //printk("%s hw_init reset wifi rx\n", rx_intf_compatible_str); 174 //rx_intf_api->RX_INTF_REG_RST_START_TO_EXT_write(0); 175 //rx_intf_api->RX_INTF_REG_RST_START_TO_EXT_write(4); 176 //rx_intf_api->RX_INTF_REG_RST_START_TO_EXT_write(0); 177 178 rx_intf_api->RX_INTF_REG_TLAST_TIMEOUT_TOP_write(7000); 179 //rst ddc internal module 180 for (reg_val=0;reg_val<32;reg_val++) 181 rx_intf_api->RX_INTF_REG_MULTI_RST_write(0xFFFFFFFF); 182 rx_intf_api->RX_INTF_REG_MULTI_RST_write(0); 183 rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status. will be released when openwifi_start 184 185 switch(mode) 186 { 187 case RX_INTF_AXIS_LOOP_BACK: 188 printk("%s hw_init mode RX_INTF_AXIS_LOOP_BACK\n", rx_intf_compatible_str); 189 //setting the path and mode. This must be done before our dma end reset 190 rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_write(0x15); 191 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write(1); 192 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x37);// endless mode to support sg DMA loop back, start 1 trans from sw trigger 193 194 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(num_dma_symbol_to_pl); 195 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps); 196 197 // put bb_en to constant 1 198 reg_val = rx_intf_api->RX_INTF_REG_IQ_CTRL_read(); 199 reg_val = (reg_val|0x8); 200 rx_intf_api->RX_INTF_REG_IQ_CTRL_write(reg_val); 201 202 // connect axis slave and master directly for loopback 203 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x1037); 204 205 // reset dma end point in our design 206 reg_val = rx_intf_api->RX_INTF_REG_MULTI_RST_read(); 207 reg_val = (reg_val&(~0x14) ); 208 rx_intf_api->RX_INTF_REG_MULTI_RST_write(reg_val); 209 reg_val = reg_val|(0x14); 210 rx_intf_api->RX_INTF_REG_MULTI_RST_write(reg_val); 211 reg_val = reg_val&(~0x14); 212 rx_intf_api->RX_INTF_REG_MULTI_RST_write(reg_val); 213 214 //start 1 trans now from our m_axis to ps dma 215 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(0); 216 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(1); 217 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(0); 218 break; 219 220 case RX_INTF_BW_20MHZ_AT_0MHZ_ANT0: 221 printk("%s hw_init mode DDC_BW_20MHZ_AT_0MHZ\n", rx_intf_compatible_str); 222 mixer_cfg = 0x300200F4; 223 ant_sel=0; 224 break; 225 226 case RX_INTF_BW_20MHZ_AT_0MHZ_ANT1: 227 printk("%s hw_init mode DDC_BW_20MHZ_AT_0MHZ\n", rx_intf_compatible_str); 228 mixer_cfg = 0x300200F4; 229 ant_sel=1; 230 break; 231 232 case RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0: 233 printk("%s hw_init mode DDC_BW_20MHZ_AT_N_10MHZ\n", rx_intf_compatible_str); 234 mixer_cfg = 0x300202F6; 235 ant_sel=0; 236 break; 237 238 case RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1: 239 printk("%s hw_init mode DDC_BW_20MHZ_AT_N_10MHZ\n", rx_intf_compatible_str); 240 mixer_cfg = 0x300202F6; 241 ant_sel=1; 242 break; 243 244 case RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0: 245 printk("%s hw_init mode DDC_BW_20MHZ_AT_P_10MHZ\n", rx_intf_compatible_str); 246 mixer_cfg = 0x3001F602; 247 ant_sel=0; 248 break; 249 250 case RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1: 251 printk("%s hw_init mode DDC_BW_20MHZ_AT_P_10MHZ\n", rx_intf_compatible_str); 252 mixer_cfg = 0x3001F602; 253 ant_sel=1; 254 break; 255 256 case RX_INTF_BYPASS: 257 printk("%s hw_init mode DDC_BYPASS\n", rx_intf_compatible_str); 258 mixer_cfg = 0x3001F602; 259 break; 260 261 default: 262 printk("%s hw_init mode %d is wrong!\n", rx_intf_compatible_str, mode); 263 err=1; 264 } 265 266 if (mode!=RX_INTF_AXIS_LOOP_BACK) { 267 rx_intf_api->RX_INTF_REG_MIXER_CFG_write(mixer_cfg); 268 // 0x000202F6 for: wifi ant0: -10MHz; wifi ant1: +10MHz; zigbee 4 ch ant0: -2, -7, -12, -17MHz; zigbee 4 ch ant1: +3, +8, +13, +18MHz 269 // 0x0001F602 for: wifi ant0: +10MHz; wifi ant1: -10MHz; zigbee 4 ch ant0: +3, +8, +13, +18MHz; zigbee 4 ch ant1: -2, -7, -12, -17MHz 270 // 0x0001F206 for: wifi ant0: -10MHz; wifi ant1: +10MHz; zigbee 4 ch ant0: +3, +8, +13, +18MHz; zigbee 4 ch ant1: -2, -7, -12, -17MHz 271 // 0x2101F602 for: wifi gain 4; zigbee gain 2 272 // 0xFE01F602 for: wifi gain 1/2; zigbee gain 1/4 273 // bits definitions: 274 // wifi ch selection: ant0 bit1~0; ant1 bit 9~8; ch offset: 0-0MHz; 1-5MHz; 2-10MHz; 3-15MHz(severe distortion) 275 // wifi ch +/- selection: ant0 bit2; ant1 bit 10; 0-positive; 1-negative 276 // zigbee 2M mixer +/- selection: ant0 bit3; ant1 bit 11; 0-positive; 1-negative 277 // zigbee secondary mixer +/- selection: ant0 bit4~7; ant1 bit 12~15; 0-positive; 1-negative 278 // zigbee ch slip offset: ant0 bit16; ant1 bit17; 0-select ch offset 0, 5, 10, 15; 1-select ch offset 5 10 15 20 279 // wifi gain: bit31~28; number of bits shifted to left in 2'complement code 280 // zigb gain: bit27~24; number of bits shifted to left in 2'complement code 281 // max amplitude calibration info (agc low, ddc w/o gain adj 0x0001F602): 5GHz, max amplitude 1.26e4. According to simulation, schr shrink 1bit should be enough 282 283 rx_intf_api->RX_INTF_REG_MULTI_RST_write(0); 284 rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status. will be released when openwifi_start 285 286 //rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x000); 287 rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x100); 288 //0x000-normal; 0x100-sig and fcs valid are controled by bit4 and bit0; 289 //0x111-sig and fcs high; 0x110-sig high fcs low; 0x101-sig low fcs high; 0x100-sig and fcs low 290 291 rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_write(0); 292 // 0-bw20-ch0; 1-bw2-ch0; 2-bw2-ch2; 3-bw2-ch4; 4-bw2-ch6; 5-s_axis-ch0 293 // 8-bw20-ch1; 9-bw2-ch1; 10-bw2-ch3; 11-bw2-ch5; 12-bw2-ch7; 13-s_axis-ch1 294 295 //rx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(1000|0x80000000); //0x80000000 to enable tsft and rssi gpio test magic value 296 //rx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(200*10); //0x80000000 to enable tsft and rssi gpio test magic value 297 rx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(30*200); // delayed interrupt 298 299 rx_intf_api->RX_INTF_REG_IQ_CTRL_write(0); 300 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x10025); //now bit 5 should be 1 to let pl_to_m_axis_intf decide num_dma_symbol_to_ps automatically 301 //rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x00025); //bit16 enable_m_axis_auto_rst 302 //bit2-0: source of M AXIS transfer trigger 303 // -0 fcs_valid_from_acc 304 // -1 sig_valid_from_acc 305 // -2 sig_invalid_from_acc 306 // -3 start_1trans_s_axis_tlast_trigger 307 // -4 start_1trans_s_axis_tready_trigger 308 // -5 internal state machine together with bit5 1. By parsing signal field, num_dma_symbol_to_ps can be decided automatically 309 // -6 start_1trans_monitor_dma_to_ps_start_trigger 310 // -7 start_1trans_ext_trigger 311 //bit3: 1-fcs valid and invalid both connected; 0-only fcs valid connected (fcs_invalid_mode) 312 //bit4: 1-num_dma_symbol_to_pl from monitor; 0-num_dma_symbol_to_pl from slv_reg8 313 //bit5: 1-num_dma_symbol_to_ps from monitor; 0-num_dma_symbol_to_ps from slv_reg9 314 //bit6: 1-pl_to_m_axis_intf will try to send both ht and non-ht; 0-only send non-ht 315 //bit8: 1-endless S AXIS; 0-normal 316 //bit9: 1-endless M AXIS; 0-normal 317 //bit12: 1-direct loop back; 0-normal 318 //bit16: 1-auto m_axis rst (sig_valid_from_acc|sig_invalid_from_acc|ht_sig_valid|ht_sig_invalid|ht_unsupported); 0-normal 319 //bit24: 1-disable m_axis fifo_rst_by_fcs_invalid; 0-enable 320 //bit29,28: sig_valid_mode. 0- non-ht sig valid; 1- ht sig valid other- both 321 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(0); 322 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write(0); 323 // 0-wifi_rx packet out; 1-loopback from input of wifi_rx 324 325 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(num_dma_symbol_to_pl); 326 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps); 327 rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_write(1<<8); 328 rx_intf_api->RX_INTF_REG_ANT_SEL_write(ant_sel); 329 330 rx_intf_api->RX_INTF_REG_MULTI_RST_write(0x14);//rst m/s axis 331 rx_intf_api->RX_INTF_REG_MULTI_RST_write(0); 332 rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status. will be released when openwifi_start 333 } 334 335 if (mode==RX_INTF_BYPASS) { 336 rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_write(0x10); //bit4 bypass enable 337 } 338 339 printk("%s hw_init err %d\n", rx_intf_compatible_str, err); 340 return(err); 341 } 342 343 static int dev_probe(struct platform_device *pdev) 344 { 345 struct device_node *np = pdev->dev.of_node; 346 struct resource *io; 347 int err=1; 348 349 printk("\n"); 350 351 if (np) { 352 const struct of_device_id *match; 353 354 match = of_match_node(dev_of_ids, np); 355 if (match) { 356 printk("%s dev_probe match!\n", rx_intf_compatible_str); 357 err = 0; 358 } 359 } 360 361 if (err) 362 return err; 363 364 rx_intf_api->hw_init=hw_init; 365 366 rx_intf_api->reg_read=reg_read; 367 rx_intf_api->reg_write=reg_write; 368 369 rx_intf_api->RX_INTF_REG_MULTI_RST_read=RX_INTF_REG_MULTI_RST_read; 370 rx_intf_api->RX_INTF_REG_MIXER_CFG_read=RX_INTF_REG_MIXER_CFG_read; 371 rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_read=RX_INTF_REG_IQ_SRC_SEL_read; 372 rx_intf_api->RX_INTF_REG_IQ_CTRL_read=RX_INTF_REG_IQ_CTRL_read; 373 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_read=RX_INTF_REG_START_TRANS_TO_PS_MODE_read; 374 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_read=RX_INTF_REG_START_TRANS_TO_PS_read; 375 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read=RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read; 376 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read; 377 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read; 378 rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_read=RX_INTF_REG_CFG_DATA_TO_ANT_read; 379 rx_intf_api->RX_INTF_REG_ANT_SEL_read=RX_INTF_REG_ANT_SEL_read; 380 rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_read=RX_INTF_REG_INTERRUPT_TEST_read; 381 382 rx_intf_api->RX_INTF_REG_MULTI_RST_write=RX_INTF_REG_MULTI_RST_write; 383 rx_intf_api->RX_INTF_REG_M_AXIS_RST_write=RX_INTF_REG_M_AXIS_RST_write; 384 rx_intf_api->RX_INTF_REG_MIXER_CFG_write=RX_INTF_REG_MIXER_CFG_write; 385 rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_write=RX_INTF_REG_IQ_SRC_SEL_write; 386 rx_intf_api->RX_INTF_REG_IQ_CTRL_write=RX_INTF_REG_IQ_CTRL_write; 387 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write=RX_INTF_REG_START_TRANS_TO_PS_MODE_write; 388 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write=RX_INTF_REG_START_TRANS_TO_PS_write; 389 rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write=RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write; 390 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write; 391 rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write; 392 rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_write=RX_INTF_REG_CFG_DATA_TO_ANT_write; 393 rx_intf_api->RX_INTF_REG_ANT_SEL_write=RX_INTF_REG_ANT_SEL_write; 394 rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write=RX_INTF_REG_INTERRUPT_TEST_write; 395 396 rx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write=RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write; 397 rx_intf_api->RX_INTF_REG_TLAST_TIMEOUT_TOP_write=RX_INTF_REG_TLAST_TIMEOUT_TOP_write; 398 399 /* Request and map I/O memory */ 400 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 401 base_addr = devm_ioremap_resource(&pdev->dev, io); 402 if (IS_ERR(base_addr)) 403 return PTR_ERR(base_addr); 404 405 rx_intf_api->io_start = io->start; 406 rx_intf_api->base_addr = (u32)base_addr; 407 408 printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", rx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); 409 printk("%s dev_probe base_addr 0x%08x\n", rx_intf_compatible_str,(u32)base_addr); 410 printk("%s dev_probe rx_intf_driver_api_inst 0x%08x\n", rx_intf_compatible_str, (u32)(&rx_intf_driver_api_inst) ); 411 printk("%s dev_probe rx_intf_api 0x%08x\n", rx_intf_compatible_str, (u32)rx_intf_api); 412 413 printk("%s dev_probe succeed!\n", rx_intf_compatible_str); 414 415 //err = hw_init(DDC_CURRENT_CH_OFFSET_CFG,8,8); 416 err = hw_init(RX_INTF_BW_20MHZ_AT_0MHZ_ANT0,8,8); 417 418 return err; 419 } 420 421 static int dev_remove(struct platform_device *pdev) 422 { 423 printk("\n"); 424 425 printk("%s dev_remove base_addr 0x%08x\n", rx_intf_compatible_str, (u32)base_addr); 426 printk("%s dev_remove rx_intf_driver_api_inst 0x%08x\n", rx_intf_compatible_str, (u32)(&rx_intf_driver_api_inst) ); 427 printk("%s dev_remove rx_intf_api 0x%08x\n", rx_intf_compatible_str, (u32)rx_intf_api); 428 429 printk("%s dev_remove succeed!\n", rx_intf_compatible_str); 430 return 0; 431 } 432 433 static struct platform_driver dev_driver = { 434 .driver = { 435 .name = "sdr,rx_intf", 436 .owner = THIS_MODULE, 437 .of_match_table = dev_of_ids, 438 }, 439 .probe = dev_probe, 440 .remove = dev_remove, 441 }; 442 443 module_platform_driver(dev_driver); 444 445 MODULE_AUTHOR("Xianjun Jiao"); 446 MODULE_DESCRIPTION("sdr,rx_intf"); 447 MODULE_LICENSE("GPL v2"); 448