1 /* 2 * Author: Xianjun jiao, Michael Mehari, Wei Liu 3 * SPDX-FileCopyrightText: 2019 UGent 4 * SPDX-License-Identifier: AGPL-3.0-or-later 5 */ 6 7 #include <linux/bitops.h> 8 #include <linux/dmapool.h> 9 #include <linux/dma/xilinx_dma.h> 10 #include <linux/init.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/module.h> 15 #include <linux/of_address.h> 16 #include <linux/of_dma.h> 17 #include <linux/of_platform.h> 18 #include <linux/of_irq.h> 19 #include <linux/slab.h> 20 #include <linux/clk.h> 21 #include <linux/io-64-nonatomic-lo-hi.h> 22 #include <linux/delay.h> 23 24 #include "../hw_def.h" 25 26 static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design 27 28 /* IO accessors */ 29 static inline u32 reg_read(u32 reg) 30 { 31 return ioread32(base_addr + reg); 32 } 33 34 static inline void reg_write(u32 reg, u32 value) 35 { 36 iowrite32(value, base_addr + reg); 37 } 38 39 static inline u32 OPENOFDM_RX_REG_STATE_HISTORY_read(void){ 40 return reg_read(OPENOFDM_RX_REG_STATE_HISTORY_ADDR); 41 } 42 43 static inline void OPENOFDM_RX_REG_MULTI_RST_write(u32 Data) { 44 reg_write(OPENOFDM_RX_REG_MULTI_RST_ADDR, Data); 45 } 46 static inline void OPENOFDM_RX_REG_ENABLE_write(u32 Data) { 47 reg_write(OPENOFDM_RX_REG_ENABLE_ADDR, Data); 48 } 49 static inline void OPENOFDM_RX_REG_POWER_THRES_write(u32 Data) { 50 reg_write(OPENOFDM_RX_REG_POWER_THRES_ADDR, Data); 51 } 52 static inline void OPENOFDM_RX_REG_MIN_PLATEAU_write(u32 Data) { 53 reg_write(OPENOFDM_RX_REG_MIN_PLATEAU_ADDR, Data); 54 } 55 56 static const struct of_device_id dev_of_ids[] = { 57 { .compatible = "sdr,openofdm_rx", }, 58 {} 59 }; 60 MODULE_DEVICE_TABLE(of, dev_of_ids); 61 62 static struct openofdm_rx_driver_api openofdm_rx_driver_api_inst; 63 static struct openofdm_rx_driver_api *openofdm_rx_api = &openofdm_rx_driver_api_inst; 64 EXPORT_SYMBOL(openofdm_rx_api); 65 66 static inline u32 hw_init(enum openofdm_rx_mode mode){ 67 int err=0, i; 68 69 printk("%s hw_init mode %d\n", openofdm_rx_compatible_str, mode); 70 71 switch(mode) 72 { 73 case OPENOFDM_RX_TEST: 74 { 75 printk("%s hw_init mode OPENOFDM_RX_TEST\n", openofdm_rx_compatible_str); 76 break; 77 } 78 case OPENOFDM_RX_NORMAL: 79 { 80 printk("%s hw_init mode OPENOFDM_RX_NORMAL\n", openofdm_rx_compatible_str); 81 openofdm_rx_api->power_thres = 0; 82 openofdm_rx_api->min_plateau = 100; 83 break; 84 } 85 default: 86 { 87 printk("%s hw_init mode %d is wrong!\n", openofdm_rx_compatible_str, mode); 88 err=1; 89 } 90 } 91 printk("%s hw_init input:\npower_thres %d\nmin_plateau %d\n", 92 openofdm_rx_compatible_str, 93 openofdm_rx_api->power_thres, openofdm_rx_api->min_plateau); 94 95 // 1) power threshold configuration and reset 96 openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write(0); 97 openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(100); 98 99 //rst 100 for (i=0;i<8;i++) 101 openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0); 102 for (i=0;i<32;i++) 103 openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF); 104 for (i=0;i<8;i++) 105 openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0); 106 107 printk("%s hw_init err %d\n", openofdm_rx_compatible_str, err); 108 109 reg_write(4*4,1);//enable soft decoding 110 return(err); 111 } 112 113 static int dev_probe(struct platform_device *pdev) 114 { 115 struct device_node *np = pdev->dev.of_node; 116 struct resource *io; 117 int err=1; 118 119 printk("\n"); 120 121 if (np) { 122 const struct of_device_id *match; 123 124 match = of_match_node(dev_of_ids, np); 125 if (match) { 126 printk("%s dev_probe match!\n", openofdm_rx_compatible_str); 127 err = 0; 128 } 129 } 130 131 if (err) 132 return err; 133 134 openofdm_rx_api->hw_init=hw_init; 135 136 openofdm_rx_api->reg_read=reg_read; 137 openofdm_rx_api->reg_write=reg_write; 138 139 openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write=OPENOFDM_RX_REG_MULTI_RST_write; 140 openofdm_rx_api->OPENOFDM_RX_REG_ENABLE_write=OPENOFDM_RX_REG_ENABLE_write; 141 openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write=OPENOFDM_RX_REG_POWER_THRES_write; 142 openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write=OPENOFDM_RX_REG_MIN_PLATEAU_write; 143 144 /* Request and map I/O memory */ 145 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 146 base_addr = devm_ioremap_resource(&pdev->dev, io); 147 if (IS_ERR(base_addr)) 148 return PTR_ERR(base_addr); 149 150 printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", openofdm_rx_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); 151 printk("%s dev_probe base_addr 0x%08x\n", openofdm_rx_compatible_str,(u32)base_addr); 152 printk("%s dev_probe openofdm_rx_driver_api_inst 0x%08x\n", openofdm_rx_compatible_str, (u32)&openofdm_rx_driver_api_inst); 153 printk("%s dev_probe openofdm_rx_api 0x%08x\n", openofdm_rx_compatible_str, (u32)openofdm_rx_api); 154 155 printk("%s dev_probe succeed!\n", openofdm_rx_compatible_str); 156 157 err = hw_init(OPENOFDM_RX_NORMAL); 158 159 return err; 160 } 161 162 static int dev_remove(struct platform_device *pdev) 163 { 164 printk("\n"); 165 166 printk("%s dev_remove base_addr 0x%08x\n", openofdm_rx_compatible_str,(u32)base_addr); 167 printk("%s dev_remove openofdm_rx_driver_api_inst 0x%08x\n", openofdm_rx_compatible_str, (u32)&openofdm_rx_driver_api_inst); 168 printk("%s dev_remove openofdm_rx_api 0x%08x\n", openofdm_rx_compatible_str, (u32)openofdm_rx_api); 169 170 printk("%s dev_remove succeed!\n", openofdm_rx_compatible_str); 171 return 0; 172 } 173 174 static struct platform_driver dev_driver = { 175 .driver = { 176 .name = "sdr,openofdm_rx", 177 .owner = THIS_MODULE, 178 .of_match_table = dev_of_ids, 179 }, 180 .probe = dev_probe, 181 .remove = dev_remove, 182 }; 183 184 module_platform_driver(dev_driver); 185 186 MODULE_AUTHOR("Xianjun Jiao"); 187 MODULE_DESCRIPTION("sdr,openofdm_rx"); 188 MODULE_LICENSE("GPL v2"); 189