1 // Author: Xianjun jiao, Michael Mehari, Wei Liu 2 // SPDX-FileCopyrightText: 2019 UGent 3 // SPDX-License-Identifier: AGPL-3.0-or-later 4 5 const char *sdr_compatible_str = "sdr,sdr"; 6 7 enum openwifi_fpga_type { 8 SMALL_FPGA = 0, 9 LARGE_FPGA = 1, 10 }; 11 12 enum openwifi_band { 13 BAND_900M = 0, 14 BAND_2_4GHZ, 15 BAND_3_65GHZ, 16 BAND_5_0GHZ, 17 BAND_5_8GHZ, 18 BAND_5_9GHZ, 19 BAND_60GHZ, 20 }; 21 22 // ------------------------------------tx interface---------------------------------------- 23 const char *tx_intf_compatible_str = "sdr,tx_intf"; 24 25 #define TX_INTF_REG_MULTI_RST_ADDR (0*4) 26 #define TX_INTF_REG_MIXER_CFG_ADDR (1*4) 27 #define TX_INTF_REG_WIFI_TX_MODE_ADDR (2*4) 28 #define TX_INTF_REG_IQ_SRC_SEL_ADDR (3*4) 29 #define TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR (4*4) 30 #define TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR (5*4) 31 #define TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR (6*4) 32 #define TX_INTF_REG_MISC_SEL_ADDR (7*4) 33 #define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR (8*4) 34 #define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR (9*4) 35 #define TX_INTF_REG_CFG_DATA_TO_ANT_ADDR (10*4) 36 #define TX_INTF_REG_S_AXIS_FIFO_TH_ADDR (11*4) 37 #define TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR (12*4) 38 #define TX_INTF_REG_BB_GAIN_ADDR (13*4) 39 #define TX_INTF_REG_INTERRUPT_SEL_ADDR (14*4) 40 #define TX_INTF_REG_ANT_SEL_ADDR (16*4) 41 #define TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR (21*4) 42 #define TX_INTF_REG_PKT_INFO_ADDR (22*4) 43 #define TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_ADDR (24*4) 44 45 #define TX_INTF_NUM_ANTENNA 2 46 #define TX_INTF_NUM_BYTE_PER_DMA_SYMBOL (64/8) 47 #define TX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS 3 48 49 enum tx_intf_mode { 50 TX_INTF_AXIS_LOOP_BACK = 0, 51 TX_INTF_BYPASS, 52 TX_INTF_BW_20MHZ_AT_0MHZ_ANT0, 53 TX_INTF_BW_20MHZ_AT_0MHZ_ANT1, 54 TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0, 55 TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0, 56 TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 57 TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 58 }; 59 60 const int tx_intf_fo_mapping[] = {0, 0, 0, 0,-10,10,-10,10}; 61 const u32 dma_symbol_fifo_size_hw_queue[] = {4*1024, 4*1024, 4*1024, 4*1024}; // !!!make sure align to fifo in tx_intf_s_axis.v 62 63 struct tx_intf_driver_api { 64 u32 (*hw_init)(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type); 65 66 u32 (*reg_read)(u32 reg); 67 void (*reg_write)(u32 reg, u32 value); 68 69 u32 (*TX_INTF_REG_MULTI_RST_read)(void); 70 u32 (*TX_INTF_REG_MIXER_CFG_read)(void); 71 u32 (*TX_INTF_REG_WIFI_TX_MODE_read)(void); 72 u32 (*TX_INTF_REG_IQ_SRC_SEL_read)(void); 73 u32 (*TX_INTF_REG_CTS_TOSELF_CONFIG_read)(void); 74 u32 (*TX_INTF_REG_START_TRANS_TO_PS_MODE_read)(void); 75 u32 (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read)(void); 76 u32 (*TX_INTF_REG_MISC_SEL_read)(void); 77 u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void); 78 u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void); 79 u32 (*TX_INTF_REG_CFG_DATA_TO_ANT_read)(void); 80 u32 (*TX_INTF_REG_S_AXIS_FIFO_TH_read)(void); 81 u32 (*TX_INTF_REG_TX_HOLD_THRESHOLD_read)(void); 82 u32 (*TX_INTF_REG_INTERRUPT_SEL_read)(void); 83 u32 (*TX_INTF_REG_BB_GAIN_read)(void); 84 u32 (*TX_INTF_REG_ANT_SEL_read)(void); 85 u32 (*TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read)(void); 86 u32 (*TX_INTF_REG_PKT_INFO_read)(void); 87 u32 (*TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read)(void); 88 89 void (*TX_INTF_REG_MULTI_RST_write)(u32 value); 90 void (*TX_INTF_REG_MIXER_CFG_write)(u32 value); 91 void (*TX_INTF_REG_WIFI_TX_MODE_write)(u32 value); 92 void (*TX_INTF_REG_IQ_SRC_SEL_write)(u32 value); 93 void (*TX_INTF_REG_CTS_TOSELF_CONFIG_write)(u32 value); 94 void (*TX_INTF_REG_START_TRANS_TO_PS_MODE_write)(u32 value); 95 void (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write)(u32 value); 96 void (*TX_INTF_REG_MISC_SEL_write)(u32 value); 97 void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value); 98 void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value); 99 void (*TX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value); 100 void (*TX_INTF_REG_S_AXIS_FIFO_TH_write)(u32 value); 101 void (*TX_INTF_REG_TX_HOLD_THRESHOLD_write)(u32 value); 102 void (*TX_INTF_REG_INTERRUPT_SEL_write)(u32 value); 103 void (*TX_INTF_REG_BB_GAIN_write)(u32 value); 104 void (*TX_INTF_REG_ANT_SEL_write)(u32 value); 105 void (*TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write)(u32 value); 106 void (*TX_INTF_REG_PKT_INFO_write)(u32 value); 107 }; 108 109 // ------------------------------------rx interface---------------------------------------- 110 const char *rx_intf_compatible_str = "sdr,rx_intf"; 111 112 #define RX_INTF_REG_MULTI_RST_ADDR (0*4) 113 #define RX_INTF_REG_MIXER_CFG_ADDR (1*4) 114 #define RX_INTF_REG_INTERRUPT_TEST_ADDR (2*4) 115 #define RX_INTF_REG_IQ_SRC_SEL_ADDR (3*4) 116 #define RX_INTF_REG_IQ_CTRL_ADDR (4*4) 117 #define RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR (5*4) 118 #define RX_INTF_REG_START_TRANS_TO_PS_ADDR (6*4) 119 #define RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR (7*4) 120 #define RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR (8*4) 121 #define RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR (9*4) 122 #define RX_INTF_REG_CFG_DATA_TO_ANT_ADDR (10*4) 123 #define RX_INTF_REG_BB_GAIN_ADDR (11*4) 124 #define RX_INTF_REG_TLAST_TIMEOUT_TOP_ADDR (12*4) 125 #define RX_INTF_REG_S2MM_INTR_DELAY_COUNT_ADDR (13*4) 126 #define RX_INTF_REG_ANT_SEL_ADDR (16*4) 127 128 #define RX_INTF_NUM_ANTENNA 2 129 #define RX_INTF_NUM_BYTE_PER_DMA_SYMBOL (64/8) 130 #define RX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS 3 131 132 enum rx_intf_mode { 133 RX_INTF_AXIS_LOOP_BACK = 0, 134 RX_INTF_BYPASS, 135 RX_INTF_BW_20MHZ_AT_0MHZ_ANT0, 136 RX_INTF_BW_20MHZ_AT_0MHZ_ANT1, 137 RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0, 138 RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 139 RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0, 140 RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 141 }; 142 143 const int rx_intf_fo_mapping[] = {0,0,0,0,-10,-10,10,10}; 144 145 struct rx_intf_driver_api { 146 u32 io_start; 147 u32 base_addr; 148 149 u32 (*hw_init)(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps); 150 151 u32 (*reg_read)(u32 reg); 152 void (*reg_write)(u32 reg, u32 value); 153 154 u32 (*RX_INTF_REG_MULTI_RST_read)(void); 155 u32 (*RX_INTF_REG_MIXER_CFG_read)(void); 156 u32 (*RX_INTF_REG_IQ_SRC_SEL_read)(void); 157 u32 (*RX_INTF_REG_IQ_CTRL_read)(void); 158 u32 (*RX_INTF_REG_START_TRANS_TO_PS_MODE_read)(void); 159 u32 (*RX_INTF_REG_START_TRANS_TO_PS_read)(void); 160 u32 (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read)(void); 161 u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void); 162 u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void); 163 u32 (*RX_INTF_REG_CFG_DATA_TO_ANT_read)(void); 164 u32 (*RX_INTF_REG_ANT_SEL_read)(void); 165 u32 (*RX_INTF_REG_INTERRUPT_TEST_read)(void); 166 void (*RX_INTF_REG_MULTI_RST_write)(u32 value); 167 void (*RX_INTF_REG_MIXER_CFG_write)(u32 value); 168 void (*RX_INTF_REG_IQ_SRC_SEL_write)(u32 value); 169 void (*RX_INTF_REG_IQ_CTRL_write)(u32 value); 170 void (*RX_INTF_REG_START_TRANS_TO_PS_MODE_write)(u32 value); 171 void (*RX_INTF_REG_START_TRANS_TO_PS_write)(u32 value); 172 void (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write)(u32 value); 173 void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value); 174 void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value); 175 void (*RX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value); 176 void (*RX_INTF_REG_BB_GAIN_write)(u32 value); 177 void (*RX_INTF_REG_ANT_SEL_write)(u32 value); 178 void (*RX_INTF_REG_INTERRUPT_TEST_write)(u32 value); 179 180 void (*RX_INTF_REG_M_AXIS_RST_write)(u32 value); 181 void (*RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write)(u32 value); 182 void (*RX_INTF_REG_TLAST_TIMEOUT_TOP_write)(u32 value); 183 }; 184 185 // ----------------------------------openofdm rx------------------------------- 186 const char *openofdm_rx_compatible_str = "sdr,openofdm_rx"; 187 188 #define OPENOFDM_RX_REG_MULTI_RST_ADDR (0*4) 189 #define OPENOFDM_RX_REG_ENABLE_ADDR (1*4) 190 #define OPENOFDM_RX_REG_POWER_THRES_ADDR (2*4) 191 #define OPENOFDM_RX_REG_MIN_PLATEAU_ADDR (3*4) 192 #define OPENOFDM_RX_REG_STATE_HISTORY_ADDR (20*4) 193 194 enum openofdm_rx_mode { 195 OPENOFDM_RX_TEST = 0, 196 OPENOFDM_RX_NORMAL, 197 }; 198 199 struct openofdm_rx_driver_api { 200 u32 power_thres; 201 u32 min_plateau; 202 203 u32 (*hw_init)(enum openofdm_rx_mode mode); 204 205 u32 (*reg_read)(u32 reg); 206 void (*reg_write)(u32 reg, u32 value); 207 208 u32 (*OPENOFDM_RX_REG_STATE_HISTORY_read)(void); 209 210 void (*OPENOFDM_RX_REG_MULTI_RST_write)(u32 value); 211 void (*OPENOFDM_RX_REG_ENABLE_write)(u32 value); 212 void (*OPENOFDM_RX_REG_POWER_THRES_write)(u32 value); 213 void (*OPENOFDM_RX_REG_MIN_PLATEAU_write)(u32 value); 214 }; 215 216 // ---------------------------------------openofdm tx------------------------------- 217 const char *openofdm_tx_compatible_str = "sdr,openofdm_tx"; 218 219 #define OPENOFDM_TX_REG_MULTI_RST_ADDR (0*4) 220 #define OPENOFDM_TX_REG_INIT_PILOT_STATE_ADDR (1*4) 221 #define OPENOFDM_TX_REG_INIT_DATA_STATE_ADDR (2*4) 222 223 enum openofdm_tx_mode { 224 OPENOFDM_TX_TEST = 0, 225 OPENOFDM_TX_NORMAL, 226 }; 227 228 struct openofdm_tx_driver_api { 229 u32 (*hw_init)(enum openofdm_tx_mode mode); 230 231 u32 (*reg_read)(u32 reg); 232 void (*reg_write)(u32 reg, u32 value); 233 234 void (*OPENOFDM_TX_REG_MULTI_RST_write)(u32 value); 235 void (*OPENOFDM_TX_REG_INIT_PILOT_STATE_write)(u32 value); 236 void (*OPENOFDM_TX_REG_INIT_DATA_STATE_write)(u32 value); 237 }; 238 239 // ---------------------------------------xpu low MAC controller------------------------------- 240 241 // extra filter flag together with enum ieee80211_filter_flags in mac80211.h 242 #define UNICAST_FOR_US (1<<9) 243 #define BROADCAST_ALL_ONE (1<<10) 244 #define BROADCAST_ALL_ZERO (1<<11) 245 #define MY_BEACON (1<<12) 246 #define MONITOR_ALL (1<<13) 247 248 const char *xpu_compatible_str = "sdr,xpu"; 249 250 #define XPU_REG_MULTI_RST_ADDR (0*4) 251 #define XPU_REG_SRC_SEL_ADDR (1*4) 252 #define XPU_REG_TSF_LOAD_VAL_LOW_ADDR (2*4) 253 #define XPU_REG_TSF_LOAD_VAL_HIGH_ADDR (3*4) 254 #define XPU_REG_BAND_CHANNEL_ADDR (4*4) 255 #define XPU_REG_DIFS_ADVANCE_ADDR (5*4) 256 #define XPU_REG_RSSI_DB_CFG_ADDR (7*4) 257 #define XPU_REG_LBT_TH_ADDR (8*4) 258 #define XPU_REG_CSMA_DEBUG_ADDR (9*4) 259 #define XPU_REG_BB_RF_DELAY_ADDR (10*4) 260 #define XPU_REG_MAX_NUM_RETRANS_ADDR (11*4) 261 #define XPU_REG_RECV_ACK_COUNT_TOP0_ADDR (16*4) 262 #define XPU_REG_RECV_ACK_COUNT_TOP1_ADDR (17*4) 263 #define XPU_REG_SEND_ACK_WAIT_TOP_ADDR (18*4) 264 #define XPU_REG_CSMA_CFG_ADDR (19*4) 265 266 #define XPU_REG_SLICE_COUNT_TOTAL_ADDR (20*4) 267 #define XPU_REG_SLICE_COUNT_START_ADDR (21*4) 268 #define XPU_REG_SLICE_COUNT_END_ADDR (22*4) 269 270 #define XPU_REG_CTS_TO_RTS_CONFIG_ADDR (26*4) 271 #define XPU_REG_FILTER_FLAG_ADDR (27*4) 272 #define XPU_REG_BSSID_FILTER_LOW_ADDR (28*4) 273 #define XPU_REG_BSSID_FILTER_HIGH_ADDR (29*4) 274 #define XPU_REG_MAC_ADDR_LOW_ADDR (30*4) 275 #define XPU_REG_MAC_ADDR_HIGH_ADDR (31*4) 276 277 #define XPU_REG_FC_DI_ADDR (34*4) 278 #define XPU_REG_ADDR1_LOW_ADDR (35*4) 279 #define XPU_REG_ADDR1_HIGH_ADDR (36*4) 280 #define XPU_REG_ADDR2_LOW_ADDR (37*4) 281 #define XPU_REG_ADDR2_HIGH_ADDR (38*4) 282 #define XPU_REG_ADDR3_LOW_ADDR (39*4) 283 #define XPU_REG_ADDR3_HIGH_ADDR (40*4) 284 285 #define XPU_REG_SC_LOW_ADDR (41*4) 286 #define XPU_REG_ADDR4_HIGH_ADDR (42*4) 287 #define XPU_REG_ADDR4_LOW_ADDR (43*4) 288 289 #define XPU_REG_TRX_STATUS_ADDR (50*4) 290 #define XPU_REG_TX_RESULT_ADDR (51*4) 291 292 #define XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR (58*4) 293 #define XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR (59*4) 294 295 #define XPU_REG_RSSI_HALF_DB_ADDR (60*4) 296 #define XPU_REG_IQ_RSSI_HALF_DB_ADDR (61*4) 297 298 enum xpu_mode { 299 XPU_TEST = 0, 300 XPU_NORMAL, 301 }; 302 303 struct xpu_driver_api { 304 u32 (*hw_init)(enum xpu_mode mode); 305 306 u32 (*reg_read)(u32 reg); 307 void (*reg_write)(u32 reg, u32 value); 308 309 void (*XPU_REG_MULTI_RST_write)(u32 value); 310 u32 (*XPU_REG_MULTI_RST_read)(void); 311 312 void (*XPU_REG_SRC_SEL_write)(u32 value); 313 u32 (*XPU_REG_SRC_SEL_read)(void); 314 315 void (*XPU_REG_RECV_ACK_COUNT_TOP0_write)(u32 value); 316 u32 (*XPU_REG_RECV_ACK_COUNT_TOP0_read)(void); 317 318 void (*XPU_REG_RECV_ACK_COUNT_TOP1_write)(u32 value); 319 u32 (*XPU_REG_RECV_ACK_COUNT_TOP1_read)(void); 320 321 void (*XPU_REG_SEND_ACK_WAIT_TOP_write)(u32 value); 322 u32 (*XPU_REG_SEND_ACK_WAIT_TOP_read)(void); 323 324 void (*XPU_REG_ACK_FC_FILTER_write)(u32 value); 325 u32 (*XPU_REG_ACK_FC_FILTER_read)(void); 326 327 void (*XPU_REG_CTS_TO_RTS_CONFIG_write)(u32 value); 328 u32 (*XPU_REG_CTS_TO_RTS_CONFIG_read)(void); 329 330 void (*XPU_REG_FILTER_FLAG_write)(u32 value); 331 u32 (*XPU_REG_FILTER_FLAG_read)(void); 332 333 void (*XPU_REG_MAC_ADDR_LOW_write)(u32 value); 334 u32 (*XPU_REG_MAC_ADDR_LOW_read)(void); 335 336 void (*XPU_REG_MAC_ADDR_HIGH_write)(u32 value); 337 u32 (*XPU_REG_MAC_ADDR_HIGH_read)(void); 338 339 void (*XPU_REG_BSSID_FILTER_LOW_write)(u32 value); 340 u32 (*XPU_REG_BSSID_FILTER_LOW_read)(void); 341 342 void (*XPU_REG_BSSID_FILTER_HIGH_write)(u32 value); 343 u32 (*XPU_REG_BSSID_FILTER_HIGH_read)(void); 344 345 void (*XPU_REG_BAND_CHANNEL_write)(u32 value); 346 u32 (*XPU_REG_BAND_CHANNEL_read)(void); 347 348 void (*XPU_REG_DIFS_ADVANCE_write)(u32 value); 349 u32 (*XPU_REG_DIFS_ADVANCE_read)(void); 350 351 u32 (*XPU_REG_TRX_STATUS_read)(void); 352 u32 (*XPU_REG_TX_RESULT_read)(void); 353 354 u32 (*XPU_REG_TSF_RUNTIME_VAL_LOW_read)(void); 355 u32 (*XPU_REG_TSF_RUNTIME_VAL_HIGH_read)(void); 356 357 void (*XPU_REG_TSF_LOAD_VAL_LOW_write)(u32 value); 358 void (*XPU_REG_TSF_LOAD_VAL_HIGH_write)(u32 value); 359 void (*XPU_REG_TSF_LOAD_VAL_write)(u32 high_value, u32 low_value); 360 361 u32 (*XPU_REG_FC_DI_read)(void); 362 u32 (*XPU_REG_ADDR1_LOW_read)(void); 363 u32 (*XPU_REG_ADDR1_HIGH_read)(void); 364 u32 (*XPU_REG_ADDR2_LOW_read)(void); 365 u32 (*XPU_REG_ADDR2_HIGH_read)(void); 366 367 void (*XPU_REG_LBT_TH_write)(u32 value); 368 u32 (*XPU_REG_LBT_TH_read)(void); 369 370 void (*XPU_REG_RSSI_DB_CFG_write)(u32 value); 371 u32 (*XPU_REG_RSSI_DB_CFG_read)(void); 372 373 void (*XPU_REG_CSMA_DEBUG_write)(u32 value); 374 u32 (*XPU_REG_CSMA_DEBUG_read)(void); 375 376 void (*XPU_REG_CSMA_CFG_write)(u32 value); 377 u32 (*XPU_REG_CSMA_CFG_read)(void); 378 379 void (*XPU_REG_SLICE_COUNT_TOTAL_write)(u32 value); 380 void (*XPU_REG_SLICE_COUNT_START_write)(u32 value); 381 void (*XPU_REG_SLICE_COUNT_END_write)(u32 value); 382 void (*XPU_REG_SLICE_COUNT_TOTAL1_write)(u32 value); 383 void (*XPU_REG_SLICE_COUNT_START1_write)(u32 value); 384 void (*XPU_REG_SLICE_COUNT_END1_write)(u32 value); 385 386 u32 (*XPU_REG_SLICE_COUNT_TOTAL_read)(void); 387 u32 (*XPU_REG_SLICE_COUNT_START_read)(void); 388 u32 (*XPU_REG_SLICE_COUNT_END_read)(void); 389 u32 (*XPU_REG_SLICE_COUNT_TOTAL1_read)(void); 390 u32 (*XPU_REG_SLICE_COUNT_START1_read)(void); 391 u32 (*XPU_REG_SLICE_COUNT_END1_read)(void); 392 393 void (*XPU_REG_BB_RF_DELAY_write)(u32 value); 394 void (*XPU_REG_MAX_NUM_RETRANS_write)(u32 value); 395 396 void (*XPU_REG_MAC_ADDR_write)(u8 *mac_addr); 397 }; 398